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Intel(R) E8870IO Server I/O Hub (SIOH) Datasheet
Product Features
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Scalability Port (SP): -- Two SPs with 3.2 GB/s peak bandwidth per direction per SP. -- Bi-directional SPs for a total bandwidth of 12.8 GB/s. Four Hub Interface 2.0 Ports: -- For connecting to Intel(R) 82870P2 PCI/ PCI-X 64-bit Hub 2 (P64H2). -- 16-bit, 533 MHz interface. -- 1 GB/s peak data rate. One Hub Interface 1.5 Port: -- For connecting to Intel(R) 82801DB. Legacy I/O Controller Hub 4 (ICH4). -- 8-bit, 266 MHz interface. -- 266 MB/s peak data rate. Supports peer-to-peer write traffic between Hub Interface Ports. Dedicated read cache for each Hub Interface Port: -- 32 128-byte cache lines. -- Dedicated prefetch engines for Hub Interface 2.0 ports. Supports caching of frequently used and prefetched data residing in main memory. 64-line write cache.
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Aggressive prefetching algorithm optimized for PCI-X functionality supported by the 82870P2 component: -- Utilizing enhanced features such as read-streaming, and prefetch horizon. Supports multiple unordered inbound traffic streams: -- Two unordered streams per Hub Interface 2.0 port. -- One stream for the Hub Interface 1.5 port. System Management Bus (SMBus) 2.0 slave interface for server management with Packet Error Checking. Reliability, Availability, and Serviceability (RAS): -- Sideband access to configuration registers via SMBus SMBus or JTAG. -- End-to-end ECC for all interfaces. -- Fault detection and logging. -- Signal connectivity testing via. boundary scan. Packaging: -- 42.5 mm x 42.5 mm -- 1012-pin organic LAN grid array (OLGA) package-2B.
Document Number: 251111-001 August 2002
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Itanium 2 processor, E8870 chipset and E8870IO (SIOH) component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-5484725, or by visiting Intel's website at http://www.intel.com. Intel, Itanium 2, E8870 and E8870IO are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Copyright (c) 2002, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others.
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Contents
1 Introduction......................................................................................................................1-1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 2 Overview ............................................................................................................1-1 Server I/O Hub Architectural Overview ..............................................................1-1 Interfaces............................................................................................................1-2 Scalability Port Interface.....................................................................................1-4 Hub Interface......................................................................................................1-4 SMBus Interface.................................................................................................1-4 JTAG Tap Port ...................................................................................................1-5 Terminology........................................................................................................1-5 Reference Documents........................................................................................1-6 Revision History .................................................................................................1-6
Signal Description ...........................................................................................................2-1 2.1 2.2 2.3 2.4 2.5 2.6 Conventions .......................................................................................................2-1 Scalability Port (SP) Interface ............................................................................2-1 Hub Interface 1.5................................................................................................2-3 Reset and Miscellaneous Signals ......................................................................2-4 Clock Signals......................................................................................................2-5 JTAG and SMBus Signals..................................................................................2-6 Register Access Mechanisms ............................................................................3-1 3.1.1 Scalability Port Initiated Register Access ..............................................3-1 3.1.2 JTAG Initiated Register Access.............................................................3-1 3.1.3 SMBus Operation ..................................................................................3-2 Device Mapping..................................................................................................3-2 Register Attributes..............................................................................................3-4 Vendor ID Register (VID) ...................................................................................3-4 Device ID Register (DID)....................................................................................3-5 PCI Command Registers (PCICMD) ..................................................................3-5 PCI Status Registers (PCISTS)..........................................................................3-6 Revision ID Register (RID) .................................................................................3-6 Class Code Registers (CCR) .............................................................................3-7 Header Type Registers (HDR) ...........................................................................3-7 Subsystem Vendor ID Register (SVID) ..............................................................3-7 Subsystem ID Register (SID) .............................................................................3-8 Hub Interface Control Registers (HLCTL) ..........................................................3-8 Hub Interface Command Control Registers (HLCMD) .......................................3-9 Hub Interface Recoverable Error Control Registers (RECHUB) ......................3-11 Hub Interface Recoverable Error Data Registers (REDHUB) ..........................3-12 Hub Interface Non-Recoverable Error Control Register (NRECHUB)..............3-13 Hub Interface ECC Mask Register (HECCMSK)..............................................3-13 Hub Interface Performance Monitor Response and Control Registers (HL_PMR[1:0]) .................................................................................................3-14 Hub Interface Performance Monitor Event Registers - Low (HL_PME_LO[1:0])...........................................................................................3-16 Hub Interface Performance Monitor Event Registers - High (HL_PME_HI[1:0]) ............................................................................................3-18
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Configuration Registers...................................................................................................3-1 3.1
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21
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3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.37 3.38 3.39 3.40 3.41 3.42 3.43 3.44 3.45 3.46 3.47 3.48 3.49 3.50 3.51 3.52 3.53 3.54 4
Hub Interface Performance Monitor Resource Event Registers (HL_PME_RSC[1:0])........................................................................................3-18 Hub Interface Performance Monitor Data Registers (HL_PMD[1:0]) ...............3-19 Hub Interface Performance Monitor Compare Register (HL_PMCMP[1:0])............................................................................................3-19 SIOH Control Registers (IOCTL)......................................................................3-20 System Reset Register (SYRE) .......................................................................3-21 Memory-Mapped I/O Base Low Address Register (MMIOBL) .........................3-21 Memory-Mapped I/O Limit Low Address Register (MMIOLL) ..........................3-21 Memory-Mapped I/O Segment Low Register (MMIOSL[5:0]) ..........................3-22 Memory-Mapped I/O Base High Address Register (MMIOBH) ........................3-22 Memory-Mapped I/O Limit High Address Register (MMIOLH) .........................3-23 Memory-Mapped I/O Segment High Address Register (MMIOSH[5:0])...........3-23 PCI Configuration Bus Base Register (BUSNO[5:0]).......................................3-24 SAPIC Segment Registers (SSEG[5:0]) ..........................................................3-24 I/O Link Registers (IOL[5:0]) ............................................................................3-24 Chip Boot Configuration Registers (CBC)........................................................3-25 Boot Flag Registers (BOFL) .............................................................................3-26 Scratch Pad Register (SPAD) ..........................................................................3-26 Scratch Pad Register Sticky (SPADS) .............................................................3-26 Performance Monitor Control Registers (PERFCON) ......................................3-27 SP Performance Monitor Response and Control Registers (SP_PMR[1:0]) .................................................................................................3-28 SP Performance Monitor Event Registers (SP_PME[1:0]) ..............................3-31 SP Performance Monitor Resource Event Registers (SP_PME_RSC[1:0])........................................................................................3-32 SP Performance Monitor Data Registers (SP_PMD[1:0])................................3-32 SP Performance Monitor Compare Register (SP_PMCMP[1:0]) .....................3-33 Error Command Registers (ERRCOM) ............................................................3-33 First Error Status Registers (FERRST) ............................................................3-34 Two or More Errors Status Register (SERRST)...............................................3-38 Error Mask Registers (ERRMASK) ..................................................................3-38 SPP Recoverable Error Control Register (RECSPP).......................................3-38 SPP Non-Recoverable Error Control Register (NRECSPP) ............................3-39 SP Interface Control Registers (SPINCO[1:0]) ................................................3-39 SPL Recoverable Error Control Register (RECSPL[1:0]) ................................3-41 SPL Recoverable Error Data Registers (REDSPL[1:0])...................................3-41
Address Map ...................................................................................................................4-1 4.1 Address Ranges.................................................................................................4-1 4.1.1 Memory-Mapped I/O .............................................................................4-1 4.1.2 I/O Space ..............................................................................................4-3 4.1.3 SAPIC/IOAPIC and PCI Hot-Plug Ranges ............................................4-4 4.1.4 Compatibility Bus .................................................................................. 4-6 4.1.5 VGA Space ...........................................................................................4-6 Illegal Addresses ................................................................................................4-6
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Clocking .......................................................................................................................... 5-1 5.1 5.2 5.3 5.4 SIOH Clocking....................................................................................................5-1 Reference Clock (SYSCLK) ...............................................................................5-1 Clock Outputs.....................................................................................................5-2 Feedback and Matching.....................................................................................5-2
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5.5 5.6 5.7 5.8 5.9 6 6.1 6.2
JTAG Test Access Port ......................................................................................5-2 SMBus Clocking .................................................................................................5-2 Spread Spectrum Support..................................................................................5-2 No Stop Clock or Thermal Shutdown .................................................................5-2 Deterministic Systems........................................................................................5-3 Reset Sequence Overview.................................................................................6-1 Power-Up Sequence ..........................................................................................6-2 6.2.1 PWRGOOD Deasserted........................................................................6-2 6.2.2 PWRGOOD Assertion ...........................................................................6-2 6.2.3 First RESETI# Deassertion ...................................................................6-2 Hard Reset .........................................................................................................6-2 6.3.1 Hard Reset Assertion ............................................................................6-3 6.3.2 Hard Reset Deassertion ........................................................................6-3 6.3.3 Non-Existent Hub Interface Devices .....................................................6-3 Reset Signals .....................................................................................................6-4 6.4.1 PWRGOOD ...........................................................................................6-4 6.4.2 RESETI# ...............................................................................................6-4 6.4.3 RESET66# ............................................................................................6-4 6.4.4 DET .......................................................................................................6-4 Data Integrity ......................................................................................................7-1 7.1.1 End-to-End Error Correction..................................................................7-1 7.1.2 Error Reporting......................................................................................7-2 7.1.3 Interface Details ....................................................................................7-4 7.1.4 Time-Out ...............................................................................................7-5 Non-Operational Maximum Rating .....................................................................8-1 Operational Power Delivery Specification ..........................................................8-1 Scalability Port (SP) Signal Group .....................................................................8-2 Hub Interface 2.0 (HI 2.0) Signal Group.............................................................8-3 8.4.1 Hub Interface 2.0 DC Specifications .....................................................8-3 Hub Interface 1.5 (HI 1.5) Signal Group.............................................................8-4 8.5.1 HI 1.5 Signal Groups .............................................................................8-4 8.5.2 Hub Interface 1.5 DC Specifications .....................................................8-4 Analog Inputs .....................................................................................................8-5 8.6.1 Hub Interface Impedance Compenstation (RCOMP) ............................8-5 8.6.2 Hub Interface Vref/Vswing Decoupling..................................................8-6 SMBus and TAP Signal Group...........................................................................8-6 8.7.1 SMBus and TAP DC Specifications ......................................................8-7 8.7.2 SMBus and TAP AC Specifications.......................................................8-8 8.7.3 SMBus and TAP AC Timing Waveforms...............................................8-9 Miscellaneous Signal Group...............................................................................8-9 8.8.1 Miscellaneous Signal DC Specifications .............................................8-10 8.8.2 Miscellaneous Signal AC Specifications .............................................8-11 Clock Signal Groups.........................................................................................8-12 8.9.1 AC Specification ..................................................................................8-13
Reset ...............................................................................................................................6-1
6.3
6.4
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Reliability, Availability and Serviceability (RAS) ..............................................................7-1 7.1
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Electrical Specifications...................................................................................................8-1 8.1 8.2 8.3 8.4 8.5
8.6
8.7
8.8
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Package and Ballout .......................................................................................................9-1 9.1 9.2 9.3 1012-Ball OLGA2b Package Information ...........................................................9-1 Ballout - Signal List............................................................................................ 9-4 Signal - Ball Number List .................................................................................9-17
Figures
1-1 1-2 1-3 4-1 4-2 4-3 5-1 6-1 8-1 8-2 8-3 8-4 9-1 9-2 9-3 Typical Intel(R) E8870 Chipset-Based Eight-Way Itanium(R) 2 Server System Configuration .........................................................................................1-2 SIOH Interfaces..................................................................................................1-3 SIOH Functional Blocks .....................................................................................1-3 SIOH Memory-Mapped I/O Space Example ......................................................4-2 SIOH I/O Space .................................................................................................4-3 SIOH SAPIC Space ...........................................................................................4-5 SIOH Platform Clocking Example ......................................................................5-1 SIOH Reset Sequence.......................................................................................6-1 TAP DC Thresholds ...........................................................................................8-7 TAP and SMBus Valid Delay Timing Waveform ................................................8-9 TCK and SM_CLK Clock Waveform ..................................................................8-9 Generic Differential Clock Waveform ...............................................................8-13 1012-Ball OLGA2b Package Dimensions - Top View .......................................9-1 1012-Ball OLGA2b Package Dimensions - Bottom View ..................................9-2 1012-Ball OLGA2b Solder Ball Detail ................................................................9-3
Tables
1-1 2-1 2-2 2-3 2-4 2-5 2-6 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 6-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9
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Chipset Component Markings ............................................................................1-1 Scalability Port (SP) Signals ..............................................................................2-1 Hub Interface 2.0 Signals ...................................................................................2-3 Hub Interface 1.5 Signals ...................................................................................2-3 Reset and Miscellaneous Signals ......................................................................2-4 Input and Output Clock Signals..........................................................................2-5 JTAG and SMBus Signals.................................................................................. 2-6 JTAG Read to Configuration Space...................................................................3-1 JTAG Write to Configuration Space ...................................................................3-2 Outbound Configuration Cycle Routing.............................................................. 3-3 SIOH Function Mapping.....................................................................................3-3 Register Attributes Definitions ............................................................................3-4 Error Log Register Grouping ............................................................................3-37 Memory-Mapped I/O Cycle Routing...................................................................4-2 I/O Cycle Routing ...............................................................................................4-4 I/O Space Programming Example......................................................................4-4 SAPIC/IOAPIC and PCI Hot-Plug Cycle Routing...............................................4-5 Power-Up and Hard Reset Timings ...................................................................6-1 Absolute Maximum Non-Operational DC Ratings at the Package Pin...............8-1 Voltage and Current Specifications....................................................................8-1 Scalability Port Interface Signal Group .............................................................. 8-2 Hub Interface 2.0 Signal Groups........................................................................ 8-3 Hub Interface 2.0 DC Parameters ......................................................................8-3 Hub Interface 2.0 Reference Voltages ...............................................................8-4 Hub Interface 1.5 Signal Group..........................................................................8-4 Hub Interface 1.5 DC Signaling Specifications ..................................................8-4 SIOH Hub Interface 1.5 Reference Voltages .....................................................8-5
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8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 8-28 9-1 9-2
Table of Values for the RCOMP Resistor...........................................................8-5 SMBus and TAP Interface Signal Group ...........................................................8-6 TAP Signal Terminations....................................................................................8-6 TAP DC Parameters ..........................................................................................8-7 SMBus DC Parameters ......................................................................................8-7 SMBus Signal Group AC Specifications ............................................................8-8 TAP Signal Group AC Specifications ................................................................8-8 Miscellaneous Signal Group...............................................................................8-9 VREFFBCLK66 Reference Voltage .................................................................8-10 CMOS 1.3V DC Parameters ............................................................................8-10 CMOS 1.5V Open Drain DC Parameters ........................................................8-10 CMOS 1.5V DC Parameters ...........................................................................8-11 CMOS 1.3V Open Drain AC Parameters .........................................................8-11 CMOS 1.5V Open Drain AC Parameters .........................................................8-11 CMOS 1.5V Input AC Parameters....................................................................8-12 CMOS 1.5 I/O Open Drain AC Parameters......................................................8-12 Clock Signal Groups.........................................................................................8-12 LVHSTL Clock DC Parameters ........................................................................8-13 LVHSTL Differential Clock AC Specification ....................................................8-13 SIOH Ball List .....................................................................................................9-4 SIOH Signal - Ball Number..............................................................................9-17
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Intel(R) E8870IO Server I/O Hub (SIOH) Datasheet
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Introduction
1.1 Overview
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The Intel(R) E8870 chipset delivers new levels of availability, features, and performance for servers. It provides flexible common modular architecture support for the Intel(R) Itanium(R) 2 processor family. The E8870 chipset up to four processors in a single node configuration, and up to eight processors in a multi-node configuration using the Scalability Port Switch (SPS) component, delivering stability to platforms through reuse and common architecture support. The component names used throughout this document refer to the component markings listed in Table 1-1. Table 1-1. Chipset Component Markings
Component Name SNC SIOH SPS DMH P64H2 ICH4 FWH Product Marking E8870 E8870IO E8870SP E8870DH 82870P2 82801DB 82802AC
1.2
Server I/O Hub Architectural Overview
The Intel(R) E8870IO Server I/O Hub (SIOH) component provides connectivity between the I/O bridge components and the other components in the E8870 chipset. The SIOH is capable of interfacing to a total of five I/O bridges via Hub Interface ports. The E8870 chipset may include up to two SIOH components, depending on the configuration. The example in Figure 1-1 illustrates a typical eight-way configuration. A four-way single node configuration would consist of one SIOH and one SNC component. The SIOH is capable of interfacing up to four P64H2 I/O bridge devices via the 16-bit Hub Interface 2.0 compliant ports. The 8-bit Hub Interface 1.5 compliant port is used to connect an ICH4 bridge device, providing legacy I/O functionality. Note: One ICH4 is used in both single and multi-node configurations.
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Introduction
Figure 1-1. Typical Intel(R) E8870 Chipset-Based Eight-Way Itanium(R) 2 Server System Configuration
Processor
Processor
Processor
Processor
Processor
Processor
Processor
Processor
Flash BIOS
SNC (Scalable Node Controller)
Memory
Flash BIOS
SNC (Scalable Node Controller)
Memory
S P (Scalability Port) Switch
S P (Scalability Port) Switch
SIOH (Serv er Input/Output Hub)
HI 1.5 Port
ICH4 I/O Bridge
Flash BIOS
SIOH (Serv er Input/Output Hub)
32-bit, 33MHz PCI 4x HI 2.0 Ports Super I/O USB 2.0 P64H2 PCI/PCI-X Bridge IDE CD-ROM BMIDE HDDs P64H2 PCI/PCI-X Bridge 4x HI 2.0 Ports
64-bit, 33/66/ 100/133 MHz
64-bit, 33/66/ 100/133 MHz
001247
1.3
Interfaces
The SIOH component functions as a hub between multiple I/O ports (Hub Interfaces) and the other host bridge components. The SIOH connects the multiple I/O ports to the memory subsystem, the host processors, and other SIOH components. This section provides an overview of the SIOH functionality as three high-level functional blocks:
* Hub Interface * Internal Interconnect * Scalability Port Interface
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Introduction
Refer to Figure 1-2 and Figure 1-3. Figure 1-2. SIOH Interfaces
Scalability Port Scalability Port
Write Cache
Hub Interface Rev. 1.5 Compliant
Traffic Routing
Read Cache Hub Interface (8-bit)
Read Cache
Read Cache
Read Cache
Read Cache
SIOH
Hub Interface (16-bit) Hub Interface (16-bit) Hub Interface (16-bit) Hub Interface (16-bit) Hub Interface Rev. 2.0 Compliant
001125
The SIOH is responsible for routing traffic between the different Hub Interfaces and Scalability Ports. Figure 1-3. SIOH Functional Blocks
Scalability Port Scalability Port
Scalability Port Interface
Hub Interface Rev. 1.5 Compliant
Config Registers
Internal Interconnect
Hub Interface
Hub Interface (8-bit)
Hub Interface
Hub Interface
Hub Interface
Hub Interface SIOH
Hub Interface 16-bit
Hub Interface 16-bit
Hub Interface 16-bit
Hub Interface 16-bit
Hub Interface Rev. 2.0 Compliant
001152
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Introduction
1.4
Scalability Port Interface
The Scalability Port (SP) interface is responsible for accepting and sending packets between the SIOH and either the SPS or SNC components. The SIOH SP interface consists of two SP ports. The SP is a cache-coherent interface optimized for scalable multi-node systems that maintain coherency between all processors and their caches. The SP uses a point-to-point bus topology using source-synchronous data transfer. In order to reduce pin counts, the SP uses Simultaneous Bi-directional (SBD) signalling technology. SBD technology eliminates any arbitration delays since data can be transmitted in both directions simultaneously. The SP interface includes a 40-bit data interface (32-bits of data and 8-bits of ECC) operating at 800MHz, resulting in 3.2 GB/s in each direction per SP.
1.5
Hub Interface
The Hub Interface is responsible for accepting and sending Hub Interface packets between the SIOH and an I/O bridge. The I/O bridges supported are P64H2 (Hub Interface-to-PCI bridge), ICH4 (Hub Interface-to-Compatibility bridge). For the SIOH, there are four Hub Interface 2.0 ports and one 8-bit Hub Interface 1.5 port. All Hub Interface ports support parallel termination. Parallel termination is required for the routing distances required for E8870 chipset-based platforms. Hub Interface uses a point-to-point bus topology using source-synchronous data transfer. Hub Interface uses impedance matching techniques (RCOMP) for optimal signal integrity. It dynamically adjusts the driver impedance to match the impedance of the traces on the board throughout thermal variations. Impedance adjustment is accomplished using a dedicated pin (HLxRCOMP) connected to an external resistor that equals the impedance of the Hub Interface traces. For optimal scalability, the Hub Interface cluster is replicated for each Hub Interface port.
1.6
SMBus Interface
The SIOH supports a SMBus 2.0 compatible slave interface to provide register visibility for a server management subsystem. This low cost port is a two-pin (SDA, SCL) serial interface useful for communicating with a baseboard management controller. The interface supports 100 kHz. The interface allows for a multi-master subsystem, which means more than one device can initiate data transfers at the same time. To support this feature, the SMBus bus arbitration relies on the wired-AND connection of all SMBus interfaces. Two masters can drive the bus simultaneously provided they are driving identical data. The first master drives SDA high, while another master drives SDA low loses the arbitration. The SCL signal consists of a synchronized combination of clocks generated by the masters using the wired-AND connection to the SCL signal. The SMBus serial operation uses an open-drain wired-AND bus structure that allows multiple devices to drive the bus lines and to communicate status about events such as arbitration, wait states, error conditions and so on. For example, when the slave is unable to accept or drive data at the rate that the master is requesting, the slave can hold the clock line low between the high states to insert a wait interval. The master's clock can only be altered by a slower slave peripheral keeping the clock line low or by another master during arbitration.
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Introduction
1.7
JTAG Tap Port
The SIOH supports the IEEE 1149.1 (JTAG) Test Access Port (TAP) for test and debug. The TAP interface is a serial interface comprised of five signals: TDI, TDO, TMS, TCK, and TRST#. The JTAG interface will operate from 4 to 25 MHz.
1.8
Terminology
Differential Direct Connect/Single Node Input buffer logic that requires a voltage reference or the signal complement. Up to 4-way Itanium(R) 2 processor/E8870 chipset platform configuration that consists of one SIOH and SNC that are directly connected by Scalability Ports. The SNC or SIOH that owns a modified cache line. Firmware Hub. This is the chipset Flash Memory component that typically provides the BIOS firmware code. A transaction initiated by one of the P64H2 PCI/PCI-X buses destined for a target on the other PCI/PCI-X bus on the same P64H2. The SNC that controls the memory on which a particular cache line resides. 3.3V CMOS I/O buffer logic. Transactions initiated on Hub Interface destined for the Scalability Port interface. Inverted GTL buffer logic. I/O Advanced Programmable Interrupt Controller. Intel authored an interrupt specification that covers various methods for interrupting a host processor. Each I/O bridge contains an IOxAPIC controller for issuing these interrupts on behalf of their child devices. A transaction initiated by one of the P64H2 PCI buses destined for a target on another Hub Interface port on the same SIOH. Low Voltage High Speed Tranceiver Logic Low Voltage Positive Emitter Coupled Logic Transactions initiated on a Scalability Port destined for Hub Interface. Physical unit of data transfer consisting of 40 bits of protocol level information. PCI Hot-Plug. A transaction initiated by one of the P64H2 PCI buses destined for a target on another Hub Interface port on a different SIOH.
Dirty Node FWH Hinted Peer-to-Peer
Home Node HVCMOS Inbound Transactions iGTL IOxAPIC
Local Peer-to-Peer LVHSTL LVPECL Outbound Transactions Phit PHP Remote Peer-to-Peer
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Introduction
SAPIC
Streamlined Advanced Programmable Interrupt Controller. Implemented in Itanium(R) 2 processor-based platforms, this interrupt mechanism uses inbound writes to specific addresses to interrupt the host processor. I/O APIC Controller and Hot Plug Controller Range. Simultaneous Bi-Directional. Server I/O Hub. This component is used for server platform configurations requiring high bandwidth and high connectivity I/O bus connectivity. Scalable Node Controller. Includes the processor, memory, and Scalability Port interfaces. Scalability Port. Low speed SP I/O buffer logic. Scalability Port Switch. The crossbar/central snoop filter that connects the SNCs and SIOHs.
SAR SBD SIOH
SNC SP SPCMOS SPS
1.9
Reference Documents
* * * * * * * *
Intel(R) E8870 Scalable Node Controller (SNC) Datasheet Intel(R) E8870DH DDR Memory Hub (DMH) Datasheet Intel(R) E8870SP Scalability Port Switch (SPS) Datasheet Intel(R) 82870P2 64-bit Hub 2 (P64H2) Datasheet Intel(R) 82801DB I/O Controller Hub4 (ICH4) Datasheet SMBus Specification, Revision 2.0 PCI Local Bus Specification, Revision 2.2 PCI-X Local Bus Specification, Revision 1.0
1.10
Revision History
Revision Number -001 Initial release of the document.
Description
Date August 2002
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Signal Description
2.1 Conventions
2
The terms assertion and deassertion are used extensively when describing signals, to avoid confusion when working with a mix of active-high and active-low signals. The term assert, or assertion, indicates that the signal is active, independent of whether the active level is represented by a high or low voltage. The term deassert, or deassertion, indicates that the signal is inactive. Signal names may or may not have a "#" appended to them. The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name the signal is asserted when at the high voltage level. The exception to the "#" symbol convention lies in the Hub Interface 1.5 signal description. Active is not applicable to HI 1.5. The reader is cautioned against attaching any meaning to the "#" symbol in HI 1.5 mode. When discussing data values used inside the component, the logical value is used; i.e. a data value described as "1101b" would appear as "1101b" on an active-high bus and as "0010b" on an activelow bus. When discussing the assertion of a value on the actual pin, the physical value is used; i.e. asserting an active-low signal produces a "0" value on the pin. The following notations are used to describe the signal types:
* * * *
I: O: I/O:
Input pin Output pin Bi-directional (input/output) pin
ASYNC: Asynchronous pin
2.2
Scalability Port (SP) Interface
The SP is the interface between the SIOH to the SPS and SNC components of the E8870 chipset (refer to Table 2-1).
Table 2-1. Scalability Port (SP) Signals
Signal Name SP{0/1}ZUPD[1:0] SP{0/1}SYNC Type I Analog I/O CMOS1.5 Clock Domain N/A ASYNC Description Impedance Update: Used to adjust the impedance of I/O drivers. Reset Synchronization: Provides synchronization between ports for impedance control and reference voltage adjustment. This signal is also used by the SP reset logic to determine when SP comes out of reset. SP{0/1}SYNC is released when ports at both ends of the link are ready. SP{0/1}PRES I CMOS1.5 N/A SP Present: Signals the SP of an impending hot-plug event.
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Signal Description
Table 2-1. Scalability Port (SP) Signals (Continued)
Signal Name SP{0/1}AVREFH[3:0] SP{0/1}AVREFL[3:0] SP{0/1}ASTBP[1:0] SP{0/1}ASTBN[1:0] SP{0/1}AD[15:0] Type I Analog I Analog I/O SBD I/O SBD I/O SBD I/O SBD Clock Domain N/A N/A 400 MHz 400 MHz 800 MHz Description Strand A Voltage Reference High: 3/4 VCC reference. Strand A Voltage Reference Low: 1/4 VCC reference. Strand A P Strobes: Positive phase data strobes for Strand A to transfer data at the 2x rate (800 MHz). Strand A N Strobes: Negative phase data strobes for Strand A to transfer data at the 2x rate (800 MHz). Strand A Data Bus: 16-bits of the data portion of a PHIT on Strand A. These bits are SSO encoded. SP{0/1}ASSO determines if these are out of an inverter or not. Strand A Parity/ECC: Two of these signals carry the ECC information for the data flits (AEP[1:0]). There are four bits of ECC for each data PHIT. The header flits are not ECC protected. The third signal is for parity (AEP[2]). Each PHIT is always protected by two bits of parity. Strand A Link Layer Control: For each PHIT these signals carry two of the four bits of link layer control information. Strand A SSO Encode: This signal is asserted to indicate that the data bits over Strand A are inverted. Strand B Voltage Reference High: 3/4 VCC reference. Strand B Voltage Reference Low: 1/4 VCC reference. Strand B P Strobes: Positive phase data strobes for Strand B to transfer data at the 2x rate (800 MHz). Strand B N Strobes: Negative phase data strobes for Strand B to transfer data at the 2x rate (800 MHz). Strand B Data Bus: 16-bits of the data portion of a PHIT on Strand B. These bits are SSO encoded. SP{0/1}BSSO determines if these are out of an inverter or not. Strand B Parity/ECC: Two of these signals carry the ECC information for the data flits (BEP[1:0]). There are 4-bits of ECC for each data PHIT. The header flits are not ECC protected. The third signal is for parity (BEP[2]). Each PHIT is always protected by two bits of parity. Strand B Link Layer Control: For each PHIT these signals carry two of the four bits of link layer control information. Strand B SSO Encode: This signal is asserted to indicate that the data bits over Strand B are inverted. General Purpose I/O Signals: These pins are asynchronous open drain I/O signals. To filter glitches on the inputs, the value of the input only changes when the same value has been sampled over four consecutive 200 MHz clock cycles. Similarly, to ensure accurate sampling of these signals by other devices, the output value will be asserted for a minimum of 6 consecutive 200 MHz cycles. VCC for the SP.
SP{0/1}AEP[2:0]
800 MHz
SP{0/1}ALLC
I/O SBD I/O SBD
800 MHz
SP{0/1}ASSO
800 MHz
SP{0/1}BVREFH[3:0] SP{0/1}BVREFL[3:0] SP{0/1}BSTBP[1:0] SP{0/1}BSTBN[1:0] SP{0/1}BD[15:0]
I SBD I SBD I/O SBD I/O SBD I/O SBD I/O SBD
N/A N/A 400 MHz 400 MHz 800 MHz
SP{0/1}BEP[2:0]
800 MHz
SP{0/1}BLLC
I/O SBD I/O SBD I/O CMOS 1.5 OD
800 MHz
SP{0/1}BSSO SP{0/1}GPIO[1:0]
800 MHz ASYNC
Vccsp
Analog
N/A
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Signal Description
The Hub Interface 2.0 connects the SIOH to a maximum of four P64H2 PCI/PCI-X bridge components (refer to Table 2-2). Table 2-2. Hub Interface 2.0 Signals
Signal Name HL{4/3/2/1}PD[17:0] HL{4/3/2/1}PSTRBF HL{4/3/2/1}PUSTRBF Type I/O iGTL I/O iGTL Clock Domain 533 MHz 533 MHz Description Packet data signals: PD[16] is connected to PD[20] on P64H2, and PD[17] is connected to PD[21] on P64H2. Hub Interface Strobe First: HL{n}PSTRBF strobes are used for HL{n}PD[7:0] & HL{n}PD[16]. HL{n}PUSTRBF strobes are used for HL{n}PD[15:8] & HL{n}PD[17]. HL{4/3/2/1}PSTRBS HL{4/3/2/1}PUSTRBS I/O iGTL 533 MHz Hub Interface Strobe Second: HL{n}PSTRBS strobes are used for HL{n}PD[7:0] & HL{n}PD[16]. HL{n}PUSTRBS are the strobes used for HL{n}PD[15:8] & HL{n}PD[17]. HL{4/3/2/1}RQOUT HL{4/3/2/1}RQIN HL{4/3/2/1}STOP HL{4/3/2/1}VSWING HL{4/3/2/1}RCOMP HL{4/3/2/1}VREF O iGTL I iGTL I/O iGTL I/O Analog I/O iGTL I Analog 66 MHz 66 MHz 66 MHz N/A N/A N/A Hub Interface Request Out: This must be connected to HI[16] of the P64H2. Hub Interface Request In: This must be connected to HI[17] of the P64H2. Hub Interface Stop: This must be connected to HI[18] of the P64H2. Hub Interface voltage swing. Hub Interface Compensation: Connects to the external RCOMP resistor and used for impedance matching. Hub Interface voltage reference.
2.3
Hub Interface 1.5
The Hub Interface 1.5 connects the SIOH to the legacy I/O ICH4 component (refer to Table 2-3).
Table 2-3. Hub Interface 1.5 Signals
Signal Name HL0PD[7:0]# HL0PSTRBS HL0PSTRBF HL0RQOUT# HL0RQIN# HL0STOP# HL0PAR# Type I/O iGTL I/O iGTL I/O iGTL O iGTL I iGTL I/O iGTL I/O iGTL Clock Domain 266 MHz 266 MHz 266 MHz 66 MHz 66 MHz 66 MHz 66 MHz Packet data pins. Second PD Interface Strobe. First PD Interface Strobe. Hub Interface Request Out: This must be connected to HI[8] on ICH4. Hub Interface Request In: This must be connected to HI[9] on ICH4. Hub Interface Stop Signal: This must be connected to HI[10] on ICH4. Hub Interface Parity Signal: This must be connected to HI[11] on ICH4. Description
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Signal Description
Table 2-3. Hub Interface 1.5 Signals (Continued)
Signal Name HL0VREF[1:0] HL0RCOMP HL0VSWING Type I Analog I/O iGTL I/O Analog Clock Domain N/A N/A N/A Description Hub Interface Voltage Reference. Hub Interface Compensation: Connects to the external RCOMP resistor and used for impedance matching. Hub Interface Voltage Swing.
2.4
Reset and Miscellaneous Signals
Table 2-4. Reset and Miscellaneous Signals
Signal Name RESETI# RESET66# Type I CMOS1.5 O CMOS1.5 I CMOS1.5 O CMOS 1.5 OD I/O CMOS1.5 OD Clock Domain 200 MHz 200 MHz Description Reset Input: Reset input driven by the system. Reset 66: Reset signal output for the downstream I/O components. Synchronized to the SIOH reset input (RESETI#) signal. Power Good: Clears the SIOH. This signal is held low until all power supplies are within specification. This signal is followed by RESETI# Deassertion. Interrupt Output: SIOH interrupt output pin for SP HotPlug and performance. This pin is asynchronous and is driven for a minimum of six consecutive SYSCLKs before transitioning. ASYNC Event In/Out: Open-drain event pins connected to the performance monitors. As inputs they are used in signal conditioning the PerfMon's trigger selection. As an output they indicate that the target condition has been met for a particular monitor. To filter glitches on the inputs, the value of the input only changes when the same value has been sampled over four consecutive 200 MHz clock cycles. Similarly, to ensure accurate sampling of these signals by other devices, these output value will be asserted for a minimum of twelve consecutive 200 MHz cycles. ERR[2:0]# I/O CMOS1.5 OD I CMOS1.5 I CMOS1.5 ASYNC Error Out: Open-drain error indicator pins to indicate the severity level of an error that has occurred internally or observed by this chip. Bus Number Identification: Static inputs to set the PCI equivalent of bus ID. Device Node Identification: Static inputs to set the PCI equivalent of device ID. NODEID[3:0] specifies the SMBus slave address for the component.
PWRGOOD
ASYNC
INT_OUT#
ASYNC
EV[3:0]#
BUSID[2:0] NODEID[4:0]
N/A N/A
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Signal Description
2.5
Clock Signals
The SIOH requires a 200 MHz LVHSTL clock source. The SIOH also generates 66 MHz and 33 MHz output clocks that can be used as source clocks by the downstream I/O components (refer to Table 2-5).
Table 2-5. Input and Output Clock Signals
Signal Name SYSCLK/SYSCLK# DET Type I Differential I CMOS1.5 Clock Domain 200 MHz N/A Description System Clock: Input clock source (and complement) to the SIOH. PLL Determinism Pin: DET pin is strapped high to enable determinism in the E8870 chipset. If high, CLK33 and CLK66 references are reset on First Hard Reset Deassertion. 66 MHz Feedback Clock: External 66 MHz PLL feedback input. Voltage Reference for FBCLK66: Reference voltage for the 66 MHz PLL feedback. Clock 66: 66 MHz clock for all I/O subsystem common clock signals. Clock 33: Can be used as 33 MHz clock for ICH4 PCI bus. LVHSTL On Die Termination Enable: Enables the on die termination resistors for the LVHSTL input buffers used on clock inputs. VCC for Core clock. VSS for Core clock. VCC for SP clock. VSS for SP clock. VCC for HI clock. VSS for HI clock. VCC for Common clock. VSS for Common clock. 3.3 VCC for all HVCMOS drivers.
FBCLK66 VREFFBCLK66 CLK66 CLK33 LVHSTLODTEN
I CMOS 3.3 I Analog O CMOS 3.3 O CMOS 3.3 I CMOS1.5 Analog Analog Analog Analog Analog Analog Analog Analog Analog
66 MHz 66 MHz 66 MHz 33 MHz 200 MHz
VccaCore VssaCore VCCASP VSSASP VCCAHL VSSAHL VCCACom VSSACom Vcc33
N/A N/A N/A N/A N/A N/A N/A N/A N/A
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Signal Description
2.6
JTAG and SMBus Signals
Table 2-6. JTAG and SMBus Signals
Signal Name TCK TDI TDO TMS TRST# SCL SDA Type I JTAG I JTAG O JTAG I JTAG I JTAG I/O SMBus OD I/O SMBus OD Clock Domain TCK TCK TCK TCK ASYNC SCL SCL Description JTAG Test Clock: Clock input used to drive Test Access Port (TAP) state machine during test. TCK = 20 MHz max. JTAG Test Data In: Data input for test mode, used to serially shift data and instructions into the TAP. JTAG Test Data Out: Data output for test mode, used to serially shift data out of the TAP. JTAG Test Mode Select: This signal is used to control the state of the TAP controller. JTAG Test Reset: This signal resets the TAP controller logic. SMBus Clock: Provides synchronous operation of the SMBus. SMBus Addr/Data: Used for data transfer and arbitration on the SMBus.
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Configuration Registers
3
The SIOH is viewed by the system as a single PCI device with seven different functions. While the standard PCI header is defined in the PCI Local Bus Specification, Revision 2.2, the remaining configuration registers typically reside above 40h.
3.1
Register Access Mechanisms
The SIOH configuration registers can be accessed from the following sources:
* Configuration Read/Write from Scalability Port (SP) * System Management Bus (SMBus) * JTAG
3.1.1
Scalability Port Initiated Register Access
SIOH will accept only one configuration access from the SPs at a time. Subsequent accesses experience back pressure until the previous configuration access is finished.
3.1.2
JTAG Initiated Register Access
The SIOH provides a JTAG configuration access mechanism that allows a user to access any register in the chipset. This is accomplished by using a mechanism similar to the PCI CF8/CFC data structure. The flow to read and write configuration space via JTAG is shown in Table 3-1 and Table 3-2.
Table 3-1. JTAG Read to Configuration Space
Field of Serial Chain Data [31:0] Register Number Device Function Bus Number Error Reserved Busy Enable Access Bit# 63:32 31:24 23:19 18:16 15:8 7 6:5 4 3 Set to 1 Set to 1 Set command: Byte Enable Command 2:0 * 100 - read dword Address must be dword aligned. Poll until cleared. Read for proper termination. Write with address to read. Phase 1 Phase 2 Phase 31 Read the data.
1. Software could choose to merge Phase 2 and Phase 3 into one operation.
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Configuration Registers
Table 3-2. JTAG Write to Configuration Space
Field of Serial Chain Data [31:0] Register Number Device Function Bus Number Error Reserved Busy Enable Access Bit# 63:32 31:24 23:19 18:16 15:8 7 6:5 4 3 Set to 1 Set to 1 Set command: * 001 - write byte. Byte Enable Command 2:0 * 010 - write word Address must be word aligned. * 011 - write dword Address must be dword aligned.
1. Software could choose to merge Phase 2 and Phase 3 into one operation.
Phase 1
Phase 2
Phase 31
Write with data and address to write.
Read for proper termination.
Poll until cleared.
The bus, function, device, and register numbers are similar to the CF8 structure. This mechanism may be used in run-time and in the middle of any other traffic. Note: The JTAG port on the SIOH can only be used to access its own configuration registers.
3.1.3
SMBus Operation
The SIOH allows a server management subsystem to read and write its configuration registers. This is accomplished through an "out-of-band", slave-only SMBus 2.0 port. The SIOH claims address 11X0_XXX where XXXX specifies NODEID[3:0] pin strappings (sampled upon the deassertion of RESETI#). Note: It is possible for software to change the default Node ID by programming the CBC register. This reprogramming will not affect the SMBus address assignment.
3.2
Device Mapping
The device number for each device connected to an SP is captured from pins upon the rising edge of hard reset. In the CBC register, Bus[2:0] is captured from the BUSID[2:0] pins. Bus[7:3] are assigned by software. Bus[7:0] are intended for truly large systems where the total # of devices on the cross-bar network may exceed the 32 device limit on a given PCI bus. Software must set Bus[7:0] to FF for the SIOH when using an SP switch. Note: The compatibility bus must be programmed to Bus 0. Therefore, the SIOH Bus ID should never get assigned to 0 by software.
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Configuration Registers
In the CBC register, Node ID[4:0] are also captured from external pins on the Node ID[4:0] pins. Those bits are compared with the device number field in the PCI configuration access. The device number can be any value between 0 and 31. Software must set Node ID[4:3] to 11 in the E8870 chipset. The SIOH has a PCI bus range per Hub Interface. Each Hub Interface is assigned a bus number (BUSNO[x]) and is accessed with Type 0 configuration cycles. Bus range BUSNO[x] +1 to BUSNO[x+1] of SIOH encompasses all PCI buses behind Hub Interface[x] and is accessed with Type 1 configuration cycles. Table 3-3 describes how configuration cycles are routed by the SIOH. Table 3-3. Outbound Configuration Cycle Routing
Configuration Cycle Bus[7:0] == Bus[7:0] (in CBC) AND Device[4:0] == Node ID[4:0] Bus[7:0] == BUSNO[x]1 BUSNO[x] < Bus[7:0] < BUSNO[x+1] None of the above.
1
Route Configuration cycle targets this SIOH so service it locally and return the completion to source. Forward Type 0 configuration cycle to Hub Interface x. Forward Type 1 configuration cycle to Hub Interface x. Master Abort.
1. This test is performed only if the first row tests false.
Even if a Hub Interface is unpopulated, it must be assigned to a bus number. Any configuration cycles to this bus number will Master Abort. Table 3-4 maps the function assignments for the SIOH. Table 3-4. SIOH Function Mapping
Function Number 0 1 2 3 4 5 6 SIOH Description Hub Interface Port 0 registers (8-bit compatibility port). Hub Interface Port 1 registers. Hub Interface Port 2 registers. Hub Interface Port 3 registers. Hub Interface Port 4 registers. General SIOH registers. RAS registers.
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Configuration Registers
3.3
Register Attributes
The Default column in the following register definitions (refer to Table 3-5) indicates the register will be set to this value after a hard reset. (Refer to Chapter 6, "Reset" for the definition of a hard reset.) Start-up BIOS software is responsible for setting all register values that is dependent on the particular platform. Each of the following registers uses the following conventions for the bit attribute column. Table 3-5. Register Attributes Definitions
Attribute Read Only Read/Write Read/Write Once Abbreviation RO RW RWO Description The bit is set by the hardware only and software can only read the bit. Writes to the register have no effect. A hard reset will set the bit to its default value. The bit can be read and written by software. A hard reset will set the bit to its default value. The bit can be read by software. It can also be written by software but the hardware prevents writing it more than once without a prior hard reset. This protection applies on a bit-by-bit basis, e.g. if the RWO field is two bytes and only one byte is written, then the written byte cannot be rewritten (unless reset). However, the unwritten byte can still be written once. The bit can be either read or cleared by software. In order to clear an RC bit, the software must write a one to it. Writing a zero to an RC bit will have no effect. A hard reset will set the bit to its default value. The bit is "sticky" or unchanged by a hard reset. Read/Write, Read/Clear, and Read Only bits may be sticky. Refer to Chapter 6, "Reset" for the definition of a hard reset. These bits are only reset with PWRGOOD. This bit is reserved for future expansion and must not be written. The PCI Local Bus Specification, Revision 2.3 requires that reserved bits must be preserved. Any software that modifies a register that contains a reserved bit is responsible for reading the register, modifying the desired bits, and writing back the result.
Read/Clear
RC
Sticky
RWS, RCS, ROS RV
Reserved
3.4
Vendor ID Register (VID)
These registers latch Syndrome and ECC information for the first non-fatal error detected inside the SPL cluster. Not all errors have logs.
Device: Node_ID Function: 0, 1, 2, 3, 4, 5, 6 Offset: 00h Bit 15:0 Attr RO Default 8086h Description Vendor Identification Number: This is the standard 16-bit value assigned to Intel.
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Configuration Registers
3.5
Device ID Register (DID)
The Device ID (DID) register identifies the SIOH component and adheres to the PCI Local Bus Specification, Revision 2.2. Since this register is part of the standard PCI header, there is a DID register per PCI function.
Device: Node_ID Function: 0, 1, 2, 3, 4, 5, 6 Offset: 02h Bit 15:0 Attr RO Default Description
F0 - 0510h Device Identification Number: This value is the device ID for the SIOH F1 - 0511h component. In order for proper driver functionality, each SIOH function has a different value for the DID register. (Fn = function n). F2 - 0512h F3 - 0513h F4 - 0514h F5 - 0515h F6 - 0516h
3.6
PCI Command Registers (PCICMD)
The PCI Command (PCICMD) registers follow a subset of the PCI Local Bus Specification, Revision 2.2. These registers provide the basic control for the SIOH to initiate and respond to Hub Interface cycles and maintain compatibility with PCI configuration space. Since these registers are part of the standard PCI header, there is a PCICMD register per PCI function.
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 04h Bit 15:9 8 7 6 Attr RV RO RV RW Default 0 0 0 0 Reserved. SERR# Enable: The SIOH never issues a DO_SERR special cycle. Reserved. Parity Error Response (IERRE): Controls the SIOH response when a parity error (on function 0) or multi-bit ECC error is detected on the Hub Interface. This bit only controls the detection in PCISTS[15] and PCISTS[8]. The SIOH reports all parity errors on the Hub Interface. Refer to Section 3.47, "First Error Status Registers (FERRST)" for details on parity error reporting. 5:4 3 RV RO 0 0 Reserved. Special Cycle Enable: Controls the ability to forward PCI-type (legacy) special cycles. Devices on the Hub Interface are not capable of accepting legacy special cycles. This bit does not apply to Hub Interface specific special cycles. Bus Master Enable: Controls the ability for the SIOH to initiate Hub Interface cycles. The SIOH can always issue Hub Interface bus cycles. Memory Access Enable: Controls the ability for the SIOH to respond to memory transactions initiated on the Hub Interface. The SIOH can always accept memory transactions. I/O Access Enable: Controls the ability for the SIOH to respond to I/O transactions initiated on the Hub Interface. The E8870 chipset does not support inbound I/O cycles. Description
2 1
RO RO
1 1
0
RO
0
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Configuration Registers
3.7
PCI Status Registers (PCISTS)
The PCI Status (PCISTS) registers follow a subset of the PCI Local Bus Specification, Revision 2.2. These registers provide the basic status of this device in response to Hub Interface cycles and maintain compatibility with PCI configuration space. Since these registers are part of the standard PCI header, there is a PCISTS register per PCI function.
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 06h Bit 15 Attr RC Default 0 Description Detected Integrity Error: This bit indicates different conditions for SIOH function 0 versus functions 1 - 4. For function 0, this bit indicates that a parity error was observed on the Hub Interface. This bit is not affected by the state of PCICMD[6]. For functions 1 -4, this bit indicates that a multi-bit ECC error was detected on the Hub Interface. If PCICMD[6] is enabled, single-bit errors will also set this bit. 14 RO 0 Signalled System Error: This bit indicates if a system error special cycle (DO_SERR) is initiated by the SIOH component. This bit should never be asserted since the SIOH never initiates DO_SERR. Received Master Abort Status: This bit indicates if the SIOH receives a Master Abort completion cycle or an unimplemented Special Cycle command. Received Target Abort Status: This bit indicates if the SIOH receives a Target Abort completion cycle in response to an SIOH-initiated Hub Interface cycle. Signalled Target Abort Status: The SIOH sets this bit when it issues a Target Abort completion cycle to the Hub Interface agent. Reserved. Master Data Integrity Error: This bit indicates that a data parity or multi-bit ECC error was detected on the Hub Interface. This bit is set when all of the following conditions are met: * The SIOH detected a data parity (function 0) or multi-bit ECC error on data (functions 1 - 4) for an outbound read completion. * PCICMD[6] is set to 1. 7:0 RV 00h Reserved.
13 12
RC RC
0 0
11 10:9 8
RC RV RC
0 0 0
3.8
Revision ID Register (RID)
The Revision ID (RID) register tracks the specific revision of this component. Since this register is part of the standard PCI header, there is one RID register per PCI function.
Device: Node_ID Function: 0, 1, 2, 3, 4, 5, 6 Offset: 08h Bit 7:0 Attr RO Default XXh Revision Identification Number: 20H = C0 stepping of the SIOH 21H = C1 stepping of the SIOH Description
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Configuration Registers
3.9
Class Code Registers (CCR)
The Class Code (CCR) registers identify the SIOH component as a host bridge. These registers adhere to the PCI Local Bus Specification, Revision 2.2. Since these registers are part of the standard PCI header, there is a CCR register per PCI function.
Device: Node_ID Function: 0, 1, 2, 3, 4, 5, 6 Offset: 09h Bit 23:16 15:8 7:0 Attr RO RO RO Default 06h 00h 00h Description Base Class Code: This code indicates that the SIOH is a bridge device. Sub-Class Code: This code indicates that the SIOH bridge is part of a host bridge. Register-Level Programming Interface: This field identifies a specific programming interface that device independent software can use to interact with the device. There are no such interfaces defined for host bridges.
3.10
Header Type Registers (HDR)
The SIOH follows the standard PCI Configuration space header format and maintains seven functions. The Header-Type Registers (HDR) adhere to the PCI Local Bus Specification, Revision 2.2. Since these registers are part of the standard PCI header, there is an HDR register per PCI function.
Device: Node_ID Function: 0, 1, 2, 3, 4, 5, 6 Offset: 0Eh Bit 7 6:0 Attr RO RO Default 1 00h Description Multi-Function Device: This bit indicates if the SIOH is a multi-function device. The SIOH is a multi-function device. Configuration Layout: This field identifies the format of the standard PCI configuration header space. A value of zero indicates that it follows the standard PCI model.
3.11
Subsystem Vendor ID Register (SVID)
The Subsystem Vendor ID (SVID) register identifies the SIOH component and adheres to the PCI Local Bus Specification, Revision 2.2. Since this register is part of the standard PCI header, there is a SVID register per PCI function.
Device: Node_ID Function: 0, 1, 2, 3, 4, 5, 6 Offset: 2Ch Bit 15:0 Attr RWO Default 8086h Description Subsystem Vendor Identification Number: This value is the subsystem vendor ID for the SIOH component. The value can only be assigned once after reset.
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Configuration Registers
3.12
Subsystem ID Register (SID)
The Subsystem ID (SID) register adheres to the PCI Local Bus Specification, Revision 2.2. Since this register is part of the standard PCI header, there is a SID register per PCI function.
Device: Node_ID Function: 0, 1, 2, 3, 4, 5, 6 Offset: 2Eh Bit 15:0 Attr RWO Default 8086h Description Subsystem Identification Number: This value is the subsystem ID for the SIOH component. The value can only be assigned once after reset.
3.13
Hub Interface Control Registers (HLCTL)
These registers specify certain behavior for each Hub Interface. There is one register per interface.
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 40h Bit 15:11 10:9 Attr RV RW Default 0 0 Reserved. Inactivity Timer: These bits program the upper two bits of the Hub Interface cluster's inactivity timer. This 10-bit timer counts 200 MHz clocks and is used to determine when inbound read stream structures are active or inactive. 00 - 1.28 us 01 - 2.56 us 10 - 3.84 us 11 - 5.12 us 8 RO See Hub Interface Presence: Device detection is done via Hub Interface REQ# line. Description For function 0, presence is determined with a successful reset handshake. 0 = No device is connected on this Hub Interface 1 = A device is connected on this Hub Interface The default state of this bit depends on whether a component is present on the other end of the Hub Interface. If this interface detects that no component is present, the default state of this bit will be zero. If a component is present, the bit defaults to one. 7:6 RW 0 Outstanding Completion-Required Requests: This bit enables the number of outbound requests that require a completion the SIOH will attempt to the Hub Interface target. Such transactions include outbound read requests, outbound I/O reads and writes, and outbound configuration reads and writes. The SIOH can support up to four. The P64H2 can support four, and the ICH4 can support one. Programming this field correctly optimizes the Hub Interface bandwidth by matching the capabilities of the interfacing component. 00 - Only one outbound delayed request attempted on this Hub Interface port at a time. 01 - Two outbound delayed requests can be attempted simultaneously on this Hub Interface port. 10 - Reserved 11 - Four outbound delayed requests can be attempted simultaneously on this Hub Interface port. Each Hub Interface cluster can always accept four outbound delayed requests from the SP cluster. This register only specifies how many of those four the SIOH will attempt before waiting for the completion to return from the I/O bridge. Description
3-8
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Configuration Registers
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 40h (Continued) Bit 5 Attr RW Default 0 Description Read Streaming Disable: This bit disables the SIOH ability to use the Hub Interface 2.0 read streaming feature. For function 0, Read Streaming is not a supported feature and this bit is always read as zero. 4 RW 0 ECC/Parity Check Enable: This bit enables the ECC checking/correction logic for the Hub Interface 2.0 ports and the parity checking logic for function 0. When this bit is cleared, any ECC or parity errors detected on the Hub Interface are not reported or corrected and do not affect the routing of the packet (e.g. dropping errors on header). This bit should be enabled after the ECC/parity generation logic is enabled on the Hub Interface component. This bit does not affect the SIOH's ECC/Parity generation logic. 3 RW 0 Serial PipeID Enable: The SIOH issues outbound read requests with different PipeIDs. Setting this bit forces the SIOH to issue all outbound reads and writes with the same PipeID of 0.
2
RWS
See Disable Hub Interface: When set, this bit tri-states the corresponding Hub Description Interface outputs and masks the Hub Interface's inputs. Any internal transactions that are routed to the disabled interfaces will be master-aborted. The default state of this bit depends on whether a component is present on the other end of the Hub Interface (see HLCTL[8]). If this interface detects that a component is present, the default state of this bit will be zero. If no component is present, the bit defaults to one. Hardware does not protect against enabling an interface that does not have an interfacing component.
1
RW
0
Read Cache Disable: This bit disables the read cache for the Hub Interface. If the read caches are disabled, prefetching should also be disabled. Otherwise, the SIOH will prefetch data it will never deliver from the cache. If the read caches are disabled and the port interfaces a P64H2, restreaming also needs to be disabled in the P64H2.
0
RW
0
Prefetch Disable: This bit disables read prefetching for the Hub Interface port. If disabled, inbound reads initiated on the Hub Interface port will request only the line requested and no more.
3.14
Hub Interface Command Control Registers (HLCMD)
The Hub Interface Command/Control (HLCMD) registers specify the basic functionality of the SIOH on each Hub Interface.
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 44h Bit 31:29 Attr RO Default 0 Description HUB_SUB_FIRST: This field stores the lowest subordinate Hub Interface hub number. This information is compared with the Hub ID to determine whether a completion packet should be forwarded further down the Hub Interface hierarchy. This field is not applicable for components other than a Hub Interface-to-Hub Interface bridge. 28 RV 0 Reserved.
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Configuration Registers
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 44h (Continued) Bit 27:25 Attr RO Default 0 Description HUB_SUB_LAST: This field stores the highest subordinate Hub Interface hub number. This information is compared with the Hub ID to determine whether a completion packet should be forwarded further down the Hub Interface hierarchy. This field is not applicable for components other than a Hub Interface-to-Hub Interface bridge. 24 23:21 RV RO 0 0 Reserved. HUB_ID: This field identifies the Hub Interface ID number for the SIOH. The SIOH uses this field to determine when to accept a Hub Interface request packet and send any corresponding completion packets. This field is not applicable for components other than a Hub Interface-to-Hub Interface bridge. 20 19:16 RV RW 0 0 Reserved. HL_TIMESLICE: This field sets the Hub Interface arbiter timeslice value with four base-clock granularity. A value of zero means that the timer immediately expires and the SIOH will allow the agent interfacing Hub Interface access to the bus every other transaction. HL_WIDTH: This field sets the Hub Interface data bus width. A value of 01 indicates a 16-bit data bus and 00 indicates an 8-bit data bus. This field only applies for function 0. For functions 1 - 4 of the SIOH (Hub Interface 2.0 ports) this field is reserved and always returns 00. 13 RO 1 (0) HL_RATE_VALID: This bit is sampled by software and indicates when the Hub Interface bus rate is valid. This bit is cleared when the Hub Interface bus rate is being changed. This field only applies for function 0. For functions 1 - 4 of the SIOH (Hub Interface 2.0 ports) this field is reserved and always returns 0. 12:10 RO 010 (000) HL_RATE: This field indicates the Hub Interface data rate. Function 0 supports a 4x data rate encoded with 010. This field only applies for function 0. For functions 1 - 4 of the SIOH (Hub Interface 2.0 ports) this field is reserved and always returns 000. 9:4 3:1 RV RW 00h 111 Reserved. MAX_DATA: This field is programmed with the longest data stream the SIOH is permitted to send on the Hub Interface. MAX_DATA applies to both write request cycles and read completion cycles. 000 = 32-bytes 001 = 64-bytes 01X = 128-bytes 1XX = 256-bytes If software attempts to program HLCMD[3:1] to 000 for functions 1 to 4, any subsequent reads will return 001 indicating 64-bytes. 0 RV 0 Reserved.
15:14
RO
0
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Configuration Registers
3.15
Hub Interface Recoverable Error Control Registers (RECHUB)
These registers latch control information for the first non-fatal error detected inside the Hub Interface cluster. Not all errors have logs. This is the bit mapping for Hub Interface Requests (RECHUB[31] = 0).
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 4Ch Bit 127:120 119:112 Attr ROS (RV) ROS 0 Default 0 Description Hub Interface header ECC (Upper): This ECC code covers Header [127:64]. For function 0, this field is reserved. Hub Interface header ECC (Lower): This ECC code covers Header [63:0]. For function 0, this field is reserved except for the following bits: 114:112, which records the parity bits when AF=1 and EA = 1 (3D-word header). 113:112, which records the parity bits when AF=1 and EA = 0 (2 D-word header). 112, which records the parity bit when AF = 0 and EA = 0 (1 D-word header). 111:99 98 97:96 95:64 ROS ROS ROS ROS 0 0 0 0 Prefetch Horizon1. Reserved Field of the packet. Elen1: Extended Length. Addr[63:32]1: Address bits 63:32 of the address. The SIOH does not support all upper address bits. If the SIOH detects an inbound illegal address error because one or more of these bits are set, then Addr[63] will be set and Addr[62:32] will be zero. Addr[31:2]2: Address bits 31:2 of the address. EH: Extended Header. EA/CT: Extended Address/Configuration type. Rq/Cp: Request/completion field. R/W: Read/Write field. CR: Completion required field. AF: Address format. LK: Lock cycle. TD Routing: Transaction Description routing field. Reserved Field on the packet. TD Attribute: Transaction Descriptor Attribute. Space: Address space. Data Length: D-word data length. Byte Enables: 7:4 is the Last D-word Byte Enables and 3:0 is the First Byte Enables. Special Cycle Encoding: When Space field indicates a Special Cycle.
1. For Special Cycles, RECHUB[111:64] does not use this encoding and should be padded with zeroes by the initiator. 2. For Special Cycles, RECHUB[63:31] might have data if required by the Special Cycle. Otherwise, it should be padded with zeroes by the initiator.
63:34 33 32 31 30 29 28 27 26:21 20 19:16 15:14 13:8 7:0
ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS
0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Configuration Registers
This is the bit mapping for Hub Interface Completions (RECHUB[31] = 1).
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 4Ch Bit 127:120 119:112 111:32 31 30 29:28 27 26:21 20 19:16 15:14 13:8 7:0 Attr ROS (RV) ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS 0 0 0 0 0 0 0 0 0 0 0 0 Default 0 Description Hub interface header ECC (Upper): This ECC code covers Header[128:64]. For function 0, this field is reserved. Hub interface Header ECC (Lower): This ECC code covers Header[63:0]. For function 0, this field is reserved except for bit 112, which records the parity bit. Reserved Field on the packet. Rq/Cp: Request/completion field. R/W: Read/Write field. Reserved Field of the packet. LK: Lock cycle. TD Routing: Transaction Description routing field. Reserved Field on the packet. TD Attribute: Transaction Descriptor Attribute. Space: Address space. Data Length: D-word data length. Completion Status: Indicates the status of the request.
3.16
Hub Interface Recoverable Error Data Registers (REDHUB)
This register latches data information for the first non-fatal error detected inside the Hub Interface cluster. Not all errors have logs.
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 5Ch Bit 95:72 71:64 63:0 Attr RV ROS ROS Default 0 0 0 Reserved. ECC/Parity Field: For inbound functions 1 - 4, there are eight bits of ECC per 64 bits of data. For function 0, there is one parity bit per 32 bits of data. Data Field. Description
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Configuration Registers
3.17
Hub Interface Non-Recoverable Error Control Register (NRECHUB)
This register latches data information for the first non-fatal error detected inside the Hub Interface cluster. Not all errors have logs.
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 68h Bit 127:0 Attr ROS Default 0 Description Hub Interface Header or Internal Request/Response Header: See the RECHUB register for contents.
3.18
Hub Interface ECC Mask Register (HECCMSK)
This register is used to force an ECC error (parity for function 0) affecting only data packets flowing into the SIOH (inbound writes and outbound read completions). After this register is written with a masking function, all subsequent inbound Hub Interface data packets will generate a masked version of the ECC code. To disable testing, the mask value is left at 0h (the default). The mask is bit-wise XOR with the received ECC. Note: Even if ECC checking is disabled with the HLCTL register, this mask is still applied. For function 0 (HI1.5), only parity is supported and only HECCMSK[0] applies. This bit acts as a mask for the parity bit affecting only data packets flowing into the SIOH (inbound writes and outbound read completions). The mask is bit-wise XOR with the received parity bit.
Device: Node_ID Function: 0, 1, 2, 3, 4 Offset: 84H Bit 7:0 Attr RW Default 00h Description ECC/Parity Mask: For 64 bits of data. For function 0, bit 0 acts as a mask for the parity bit.
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Configuration Registers
3.19
Hub Interface Performance Monitor Response and Control Registers (HL_PMR[1:0])
The Performance Monitor Response (PMR) registers control operation of their associated counter, and provide overflow or max compare status information.
Device: Node_ID Function: 1, 2, 3, 4 Offset: 8Ch (HL_PMR[0]), 90h (HL_PMR[1]) Bit 31:25 24 Attr RV RW Default 0 0 Reserved. Event Register Select: The PME_LO & PME_HI registers select events based on the Hub Interface header fields. The PME_RSC register selects resource specific events that are mutually exclusive of the Hub Interface header events. One or the other of the event sets can be selected. 0 = Hub Interface events (PME_LO, PME_HI). 1 = Hub Interface resources (PME_RSC). 23:22 RW 0 Compare Mode: This field defines how the PMCMP (compare) register is to be used. 00 - Compare mode disabled (PMCMP register not used). 01 - Max compare only: The PMCMP register value is compared with the counter value. If the counter value is greater, the Count Compare Status (bit 13) of the "Event Status" field of this register will be set. 10 - Max compare with update of PMCMP at end of sample: The PMCMP register value is compared with the counter value, and if the counter value is greater, the PMCMP register is updated with the counter value. Note, the Event Status field is not affected in this mode. 11 - Address compare mode where the PMCMP register is compared with the address field. Counter 0 of a counter pair will compare on an address greater than the register, and counter 1 will compare on an address equal to or lesser than the register (inverse of greater than). When both comparisons are valid, an address range comparison qualification is generated. This mode will cause the address range comparison to be AND'ed with the event qualification specified in the selected PME register of each counter. The Event Status field is not affected in this mode. The address comparison range is A[38:7]. 21:19 RW 0 Reset Event Select: Counter and event status will reset and counting will continue. 000 - No reset condition. 001 - Partner event status: When the partner counter causes an event status condition to be activated, either by a counter overflow or max comparison, then this counter will reset and continue counting. 010 - Partner PME register event: When the partner counter detects a match condition that meets its selected PME register qualifications, then this counter will reset and continue counting. 011 - Reserved 100 - EV0 pin 101 - EV1 pin 110 - EV2 pin 111 - EV3 pin Description
3-14
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Configuration Registers
Device: Node_ID Function: 1, 2, 3, 4 Offset: 8Ch (HL_PMR[0]), 90h (HL_PMR[1]) (Continued) Bit 18:16 Attr RW Default 0 Count Event Select: This field determines the counter enable source. 000 - PME register event. 001 - Partner event status (max compare or overflow). 010 - All clocks when enabled. 011 - Reserved 100 - EV0 pin 101 - EV1 pin 110 - EV2 pin 111 - EV3 pin 15:14 RW 0 Count Mode: 00 - Count event selected by Count Event Select field. 01 - Count clocks after event selected by Count Event Select field. 10 - Count transaction length of event selected by Count Event Select field. 11 - Reserved 13:12 RW 0 Event Status: This status bit captures an overflow or count compare event. The Event Status Output field can be programmed to allow this bit to be driven to an external EV pin. x1 - Overflow -The PMD counter overflow status. 1x - Count compare - PMD counter greater than PMCMP register when in compare mode. This bit is sticky in that once an event is reported the status remains even though the original condition is no longer valid. This bit can be cleared by software or by starting a sample. Event status is always visible in the PERFCON register, except if "Event Status Output" field is in cascade mode. If in address compare mode (compare mode = 11), the count compare bit is not activated. 11:9 RW 0 Event Status Output: This field selects which pin to report event status, or an address compare if in address compare mode (compare mode = 11). 000 - Event status reported only in PERFCON register. 001 - Event status (overflow) reported to partner only. Used for cascading event counters. 100 - Event status or address comparison in PERFCON and on EV0 pin. 101 - Event status or address comparison in PERFCON and on EV1 pin. 110 - Event status or address comparison in PERFCON and on EV2 pin. 111 - Event status or address comparison in PERFCON and on EV3 pin. Description
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Configuration Registers
Device: Node_ID Function: 1, 2, 3, 4 Offset: 8Ch (HL_PMR[0]), 90h (HL_PMR[1]) (Continued) Bit 8:5 Attr RW Default 0 CD_Src: Counter disable source. These bits control which input disables the counter. Note, if the enable source is inactive, counting is also disabled. 1xxx - EV3 pin x1xx - EV2 pin xx1x - EV1 pin xxx1 - EV0 pin 4:2 RW 0 CE_Src: Counter enable source. These bits identify which input enables the counter. Default value disables counting. 000 - Disabled. 001 - PERFCON local_count_enable field. 010 - Partner event status (max compare, overflow, or cascade). 011 - Reserved 100 - EV0 pin 101 - EV1 pin 110 - EV2 pin 111 - EV3 pin 1 RW 0 Clear Overflow: This bit clears the overflow bit in the associated PMD counter. The counters continue counting. This bit is cleared by hardware when the operation is complete. Reset: Setting this bit to a one sets all registers associated with this counter to the default state. It does not change this PMR register since any desired value can be loaded while setting the Reset bit. This Reset bit will clear itself after the reset is completed. For diagnostic purposes, the contents of the other registers can be read to verify operation of this bit. There is also a reset bit in the PERFCON register that clears all counter registers including the PMR. Description
0
RW
0
3.20
Hub Interface Performance Monitor Event Registers - Low (HL_PME_LO[1:0])
Selections in these registers correspond to fields within the Hub Interface packet header. Each field selection is AND'ed with all other fields in these registers and the HL_PME_HI registers. These registers are selected for match decoding via the Event Register Select field in the PMR registers.
Device: Node_ID Function: 1, 2, 3, 4 Offset: 94h (HL_PME_LO[0]), 98h (HL_PME_LO[1]) Bit 31 30:29 Attr RW RW Default 0 0 Description Incoming/Outgoing: 0 = Incoming (from PCI bus). Request/Completion Packet: 00 - Request packet 01 - Completion packet 1x - Either
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Configuration Registers
Device: Node_ID Function: 1, 2, 3, 4 Offset: 94h (HL_PME_LO[0]), 98h (HL_PME_LO[1]) (Continued) Bit 28:27 Attr RW Default 0 Write/Read: 00 - Read 01 - Write 1x - Either read or write 26:25 RW 0 Completion Required: (Request packet only) 00 - No completion required 01 - Completion required 1x - Either 24:23 RW 0 Lock: 00 - No lock 01 - Lock 1x - Either 22:20 RW 0 TD Attributes: 0xx - Any attribute 100 - Asynchronous and snoop required 101 - Isochronous and snoop required 110 - Asynchronous and no snoop required 111 - Isochronous and no snoop required 19:18 RW 0 Configuration Type: (If Config Cycle Space selected) 00 - Type 0 01 - Type 1 1x - either type 17:16 RW 0 Prefetch: Extended header bit set in packet header and horizon field non-zero 00 - Non prefetch 01 - Prefetch 1x - Either 15:12 RW 0 Space: (OR'ed group) xxx1- Memory xx1x - IO x1xx - Configuration 1xxx - Special Cycles 11:8 RW 0 Data Length: 0xxx - Any length 1000 - 8-bytes or less 1001 - 16 bytes 1010 - 32-bytes 1011 - 64-bytes 1100 - 128-bytes 1101 - 256-bytes 1110 - 512-bytes 1111 - 1K bytes 7:0 RW 0 Completion Status (for Completion Packet) or Special Cycle Encoding (for Request Packet): 00h - Any completion status or special cycle. Description
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Configuration Registers
3.21
Hub Interface Performance Monitor Event Registers - High (HL_PME_HI[1:0])
These registers are an extension of the HL_PME_LO register. Each field selection is AND'ed with all other fields in these registers and the HL_PME_LO registers. Note that inbound retry events are AND'ed with all other match conditions. These registers are selected for match decoding via the Event Register Select field in the PMR registers.
Device: Node_ID Function: 1, 2, 3, 4 Offset: 9Ch (HL_PME_HI[0]), A0h (HL_PME_HI[1]) Bit 31:14 13:12 Attr RV RW Default 0 0 Reserved. Retry: For inbound transactions this field is AND'ed with match from all other fields, and for outbound transactions this field OR'ed with match from all other fields. Inbound vs. outbound transaction selected in bit 31 of HL_PME_LO register. 00 - All transactions selected, both retried and non-retried. x1 - Complete retry (entire inbound or outbound packet retried). 1x - Partial retry (part of packet retried - only for outbound transactions). 11:0 RW 0 Routing and Mask: "xxxxxxmmmmmm" - where x is the routing value field and m is the bit mask for each individual bit in the routing field ('1' is mask,'0' is select). Description
3.22
Hub Interface Performance Monitor Resource Event Registers (HL_PME_RSC[1:0])
These registers contain resource selections that are mutually exclusive to the event selections. These selections are not qualified by the event selections. Each individual field selection is OR'ed with the other fields to generate the counter match condition. This register is selected via the Event Register Select Field in the PMR registers.
Device: Node_ID Function: 1, 2, 3, 4 Offset: A4h (HL_PME_RSC[0]), A8h (HL_PME_RSC[1]) Bit 31:2 1:0 Attr RV RW Default 0 0 Reserved. Read Cache: 00 - Disable count 01 - Hit 10 - Miss 11 - Invalidate Description
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Configuration Registers
3.23
Hub Interface Performance Monitor Data Registers (HL_PMD[1:0])
These registers are the counter value. The overflow bit can be cleared via the PMR registers without perturbing the value of the counter. This counter is reset at the beginning of a sample period unless it has been preloaded since a prior sample.
Device: Node_ID Function: 1, 2, 3, 4 Offset: ACh (HL_PMD[0]), B0h (HL_PMD[1]) Bit 31 30:0 Attr RW RW Default 0 0 Overflow. Current counter value. Description
3.24
Hub Interface Performance Monitor Compare Register (HL_PMCMP[1:0])
The compare register can be used three ways as selected in the "Compare Mode" field of the PMR register. First, when PMD is incremented, the value of PMD is compared to the value of PMCMP. If PMD is greater than PMCMP, this status is reflected in the PERFCON register and/or on EV pins as selected in the "Event Status Output" field of the PMR register. Secondly, update the PMCMP register with the value of PMD if the PMD register exceeds the contents of PMCMP. The third mode is an address comparison mode. PMD0 compares on addresses greater than the PMCMP0 register, and PMD1 compares on addresses less than or equal to PMCMP1. The "AND" of these two comparisons is the address range comparison and it qualifies the other match event conditions for both counters. Note that the contents of PMCMP are compared to A[38:7].
Device: Node_ID Function: 1, 2, 3, 4 Offset: B4h (HL_PMCMP[0]), B8h (HL_PMCMP[1]) Bit 31:0 Attr RW Default FFFF_ FFFFh Counter compare value. Description
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Configuration Registers
3.25
SIOH Control Registers (IOCTL)
The SIOH Control Registers specify the basic functionality of the SIOH feature set.
Device: Node_ID Function: 5 Offset: 40h Bit 15 Attr RW Default 0 Description MDA Enable: This bit specifies whether or not a monochrome adapter card resides on the platform. If enabled, then any inbound writes that target B_000 to B_7FFF in legacy DOS space will get automatically routed to the compatibility bus. The monochrome adapter card (if one exists) must reside on the compatibility bus. Reserved. Multi-Node Enable: The SIOH has slightly different behavior when in a single-node configuration: 0 = Single node configuration. 1 = Multi-node configuration. In a single-node configuration, PCLR commands are never issued and Lock/PHOLD handling is different. 10 RW 1 Compatibility Bus Enable: This bit identifies if this SIOH interfaces the compatibility bus (ICH4 component). All reads or writes to the compatibility space will be routed to the 8-bit Hub Interface 1.5 port (Hub Interface port 0) if this bit is set (see Section 4.1.4, "Compatibility Bus" ). 0 = The compatibility bus does not interface this SIOH component. 1 = The compatibility bus interfaces this SIOH component (on Hub Interface port 0). 9:7 RW 000 VGA Port: This bit field identifies which Hub Interface port interfaces the VGA device for the system. All reads or writes to the legacy VGA space will be routed to the Hub Interface port specified with this field (see Section 4.1.5, "VGA Space" ). 000 = Hub Interface Port 0 (compatibility port) 001 = Hub Interface Port 1 010 = Hub Interface Port 2 011 = Hub Interface Port 3 100 = Hub Interface Port 4 101 = On Remote SIOH (forward inbound VGA accesses to SP with VGA attribute) 11x = Not on any SIOH (forward inbound VGA accesses to SP with DRAM attribute) 6 RW 0 Write Cache Flush: Setting this bit causes the SIOH to evict all write cache lines which are in Modified state. When the SIOH evicts all the Modified lines, this bit is cleared by the hardware. Software can poll this bit after setting it to know when the flush operation is complete. Reserved. ICH Destination ID Copy Disable: For interrupts issued by the ICH4, the SIOH copies address bits [19:15] to address bits [8:4]. Setting this bit disables that functionality. Reserved. Default SP: 0 = SP0 is selected as the default SP. 1 = SP1 is selected as the default SP. 1:0 RV 00 Reserved.
14:12 11
RV RW
0 0
5 4
RV RW
0 0
3 2
RV RW
0 0
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Configuration Registers
3.26
System Reset Register (SYRE)
This register allows system software to reset the SIOH component.
Device: Node_ID Function: 5 Offset: 42h Bit 7:2 1 0 Attr RV RW RW Default 0 0 0 Reserved. Boot Flag Reset: The rising edge of this bit will reset the boot flag register (BOFL) back to the default value. SIOH Reset: The rising edge on this bit will reset the entire SIOH. A reset sequence is initiated. This bit is used to reset the SIOH and asserts RESET66# during an SP Hot-Plug event. Description
3.27
Memory-Mapped I/O Base Low Address Register (MMIOBL)
The MMIOBL register with the MMIOLL register specifies one of the two address ranges allocated for Hub Interface-destined transactions. MMIOBL and MMIOLL are intended to specify a memory-mapped I/O window below the 4 GB boundary. The transaction address is compared against the base field for proper disposition. (Refer to Table 4-1 for how this register is decoded.) For comparison purposes, address bits 23:0 are ignored and 43:32 must be zero.
Device: Node_ID Function: 5 Offset: 44h Bit 7:0 Attr RW Default 00h Description Memory-Mapped I/O Base: This field specifies the lower limit for the low MMIO address range assigned to the Hub Interface buses for this and any other SIOHs in the system. These bits are compared against bits 31:24 of the transaction address. Bits 43:32 of the transaction address must be decoded as `0'.
3.28
Memory-Mapped I/O Limit Low Address Register (MMIOLL)
The MMIOBL register with the MMIOLL register specifies one of the two address ranges allocated for Hub Interface-destined transactions. MMIOBL and MMIOLL are intended to specify a memory-mapped I/O window below the 4 GB boundary. (Refer to Table 4-1 for how this register is decoded.) For comparison purposes, address bits 23:0 are ignored and 43:32 must be zero. Note: For E8870 chipset-based platforms, the upper limit of the MMIOL range is FDFF_FFFF. Therefore, this value should only be programmed to FD. (MMIOLL is inclusive for address decoding purposes.) More extensive programmability allows larger systems to implement their own address map restrictions.
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Configuration Registers
Device: Node_ID Function: 5 Offset: 45h Bit 7:0 Attr RW Default 00h Description Memory-Mapped I/O Limit: This field specifies the upper limit for the low MMIO address range assigned to the Hub Interface buses for this and any other SIOHs in the system. These bits are compared against bits 31:24 of the transaction address. Bits 43:32 of the transaction address must be decoded as `0'.
3.29
Memory-Mapped I/O Segment Low Register (MMIOSL[5:0])
The six MMIOSL registers specify the address ranges allocated for memory-mapped I/O transactions. The transaction address is compared to these boundaries for proper disposition to the low window. For comparison purposes, address bits 23:0 are ignored and 43:32 must be zero. For this decode, bits 43:32 must all be `0'. (Refer to Table 4-1 for how this register is decoded.) The memory-mapped I/O space between MMIOSL[1] and MMIOSL[0] (port 0) is defined to be the compatibility port (interface to the ICH4 legacy bridges). Note: It is assumed that the SIOH will never receive an address from a port that is destined for itself.
Device: Node_ID Function: 5 Offset: 48h, 49h, 4Ah, 4Bh, 4Ch, 4Dh Bit 7:0 Attr RW Default 00h Description Memory-Mapped I/O Segment: This field specifies the boundary between each of the five Hub Interface regions for this SIOH. These bits are compared against bits 31:24 of the transaction address.
3.30
Memory-Mapped I/O Base High Address Register (MMIOBH)
The MMIOBH registers with the MMIOLH registers specify the address range allocated for Hub Interface-destined transactions. MMIOBH and MMIOLH are intended to specify a MMIO window above the 4 GB boundary with a 64 MB granularity. The transaction address is compared against the base field for proper disposition. (Refer to Table 4-1 for how this register is decoded.) Note: High MMIO space should always be programmed above the 4 GB boundary. For comparison purposes, address bits 25:0 are ignored.
Device: Node_ID Function: 5 Offset: 50h Bit 15:0 Attr RW Default 0000h Description Memory-Mapped I/O Base: This field specifies the lower limit for the memory address range assigned to the Hub Interface buses for this and any other SIOHs in the system. These bits are compared against bits 41:26 of the transaction address.
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Configuration Registers
3.31
Memory-Mapped I/O Limit High Address Register (MMIOLH)
For comparison purposes, address bits 25:0 are ignored. MMIOLH is inclusive for address decoding purposes. (Refer to Table 4-1 for how this register is decoded.) Note: High MMIO space should always be programmed above the 4 GB boundary.
Device: Node_ID Function: 5 Offset: 52h Bit 15:0 Attr RW Default 0000h Description Memory-Mapped I/O Limit: This field specifies the upper limit for the memory address range assigned to the Hub Interface buses for this and any other SIOHs in the system. These bits are compared against bits 41:26 of the transaction address.
3.32
Memory-Mapped I/O Segment High Address Register (MMIOSH[5:0])
The six MMIOSH registers specify the address ranges allocated for memory-mapped I/O transactions. The transaction address is compared to these boundaries for proper disposition to the high window. For comparison purposes, address bits 25:0 are ignored. (Refer to Table 4-1 for how this register is decoded.) Notice that MMIOSH[0] specifies the top of the high MMIO window assigned to this SIOH component. The address compared to in this table is the transaction address from any port: five Hub Interface 2.0 ports, the Hub Interface 1.5 port, or either SP. Note: High MMIO space should always be programmed above the 4 GB boundary. For the SIOH, MMIOSH[0] and MMIOSH[1] should be programmed to the same value since the ICH4 cannot accept outbound accesses above the 4 GB boundary. It is assumed that the SIOH will never receive an address from a port that is destined for itself.
Device: Node_ID Function: 5 Offset: 54h, 56h, 58h, 5Ah, 5Ch, 5Eh Bit 15:0 Attr RW Default 0000h Description Memory-Mapped I/O Segment: This field specifies the boundary between each of the five Hub Interface regions for this SIOH. These bits are compared against bits 41:26 of the transaction address.
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Configuration Registers
3.33
PCI Configuration Bus Base Register (BUSNO[5:0])
These registers define the base (starting) PCI bus for the PCI configuration space for each Hub Interface port.
Device: Node_ID Function: 5 Offset: 60h, 62h, 64h, 66h, 68h, 6Ah Bit 15:8 7:0 Attr RV RW Default 00h 00h Reserved. Start Bus Number: The start PCI bus number of PCI configuration space to this port. This register is compared with BUS[7:0] of the configuration cycle (refer to Table 3-3). Description
3.34
SAPIC Segment Registers (SSEG[5:0])
The six SSEG registers specify the address ranges allocated for the memory-mapped I/O SAPIC, I/OAPIC, and PCI Hot-Plug regions. The transaction address is compared to these boundaries for proper disposition. For comparison purposes, address bits 43:20 are 000FECh (refer to Section 4.1.3, "SAPIC/IOAPIC and PCI Hot-Plug Ranges" for how these registers are decoded by the SIOH).
Device: Node_ID Function: 5 Offset: 70h, 72h, 74h, 76h, 78h, 7Ah Bit 15:13 12:0 Attr RV RW Default 0 0 Reserved. SAPIC Segment Register: This field specifies the boundaries between the five SAPIC/Hot-Plug regions for this SIOH. These bits are compared against bits 19:8 of the transaction address. Description
3.35
I/O Link Registers (IOL[5:0])
The IOL registers specify the address range allocated for I/O space PCI transactions. The upper five bits of the transaction address (bits 15:11) is compared against the IOL registers for proper disposition. The I/O space for a given Hub Interface port has a 2 KB granularity. If only one SIOH resides in the system, all of the 64K I/O space should be accounted for with the IOL registers. If two SIOHs reside in the system, both IOL register sets must be programmed so they do not overlap. In addition, the combination of both SIOH IOL register sets should account for the entire 64K I/O space. If there are two SIOH components in the system, IOL[0] of SIOH1 should be programmed to IOL[5] of SIOH0 (where SIOH0 interfaces the ICH4). Refer to Section 4.1.2, "I/O Space" for how these registers are decoded for proper transaction routing.
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Configuration Registers
Device: Node_ID Function: 5 Offset: 80h, 81h, 82h, 83h, 84h, 85h Bit 7:6 5:0 Attr RV RW Default 0 0 Reserved. I/O Port Base: This field specifies the base I/O address of a particular Hub Interface port. Description
3.36
Chip Boot Configuration Registers (CBC)
These registers are used to relocate this chipset's configuration space to a different PCI bus. Information captured from the idle flits is valid only when the idle detection bit in the SPINCO register is set. Note: BUS[7:0] should always be set to FF and Node ID[4:3] should always be set to 11.
Device: Node_ID Function: 5 Offset: 98h Bit 95:77 76:72 Attr RV RW Default 0 See Description 11111h See Description 0 11111h FFh 0 0 Reserved. Node ID[4:0]: These bits define the device # of this SIOH. The default value is captured from the NODEID[4:0] pins on the rising edge of hard reset. These bits are sent in the idle flits. Bus[7:3]: The top five bits of this SIOH's configuration bus number. These bits are sent in the idle flits. Bus[2:0]: The lower 3 bits of this SIOH's configuration bus number. The default value is captured from BUSID[2:0] pins on the rising edge of hard reset. These bits are sent in the idle flits. Reserved SP1 Node ID[4:0]: Device number received from SP1's idle flits. SP1 Bus[7:0]: Bus number received from SP1's idle flits. Reserved StopOnErr: 0 If an agent has detected an error and has sent an LLRReq and its local retry state machine is in RETRY_LOCAL_IDLE state, then it should not send any info or idle flits and sends a Ctrl flit with LLRIdle. 1 An agent will send idle or info flits when in RETRY_LOCAL_IDLE state. 14 RWS 0 SndMultAck: 0 LCC[7] = 0. Up to 25 ACKs will be sent in Byte D[4:0] of idle flits. Idle flits are forced whenever there are multiple acks. 1 0 or 1 ACK is sent in LCC[7] of idle flits. Byte D = 0. 13 RWS 0 RcvMultAck: 0 Up to 25 ACKs may be extracted from idle flits. Ack[4:0] = LCC[7] bit-wise OR'ed with Byte D[4:0]. Any particular idle flit will use either LCC[7] or Byte D, but not both. 1 0 or 1 ACK is extracted from LCC[7] of idle flits. 12:8 7:0 RO RO 11111h FFh SP0 Node ID[4:0]: Device number received from SP0's idle flits. SP0 Bus[7:0]: Bus number received from SP0's idle flits. Description
71:67 66:64
RW RW
63:45 44:40 39:32 31:16 15
RV RO RO RV RWS
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Configuration Registers
3.37
Boot Flag Registers (BOFL)
To reset these registers back to the default value, system software writes to the SYRE register.
Device: Node_ID Function: 5 Offset: A4h Bit 31:8 7:0 Attr RV RO Default 0 A5h Reserved. Signature: This register is used to select boot strap CPU node. The first time this register is read, it will return a non-zero signature. All reads thereafter will return zeroes. Description
3.38
Scratch Pad Register (SPAD)
This scratch pad register is available for power-on software usage before any memory is available for use.This register is used during the boot process and SP Hot-Plug.
Device: Node_ID Function: 5 Offset: B0h Bit 31:0 Attr RW Default 0 System Scratch Pad. Description
3.39
Scratch Pad Register Sticky (SPADS)
This scratch pad register is available for power-on software usage before any memory is available for use. The contents of this register remains sticky through reset. This register is used during the boot process and SP Hot-Plug.
Device: Node_ID Function: 5 Offset: B4h Bit 31:0 Attr RWS Default 0 Description System Scratch Pad: The contents of this register is sticky.
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Configuration Registers
3.40
Performance Monitor Control Registers (PERFCON)
These registers are the common control and status registers for all of the performance monitor counters in the component. They have one control to enable all counters and another control to reset all performance monitor counters and registers to their default state. One status bit for each performance monitor module (two counters per module) is reflected in this register. The PMR registers for the specific module provide detailed status information. The status bit is activated by a count comparison event or an overflow from either counter of the module.
Device: Node_ID Function: 5 Offset: BCh Bit 31:11 10 Attr RV RO Default 0 0 Reserved. SPP_PM Count Status: Status reported by the SP0_PM module. The OR of both "Event status" bits reported by either SP0_PM module for an overflow or max comparison condition. 9 RO 0 HL4_PM Count Status: Status reported by the HL3_PM module. The OR of both "Event status" bits reported by either HL3_PM module for an overflow or max comparison condition. 8 RO 0 HL3_PM Count Status: Status reported by the HL2_PM module. The OR of both "Event status" bits reported by either HL2_PM module for an overflow or max comparison condition. 7 RO 0 HL2_PM Count Status: Status reported by the HL1_PM module. The OR of both "Event status" bits reported by either HL1_PM module for an overflow or max comparison condition. 6 RO 0 HL1_PM Count Status: Status reported by the HL0_PM module. The OR of both "Event status" bits reported by either HL0_PM module for an overflow or max comparison condition. 5:2 1 RV RW 0 0 Reserved. Local Count Enable: Enables any counters on this component that have this bit assigned as the enable control in its individual PMR register. Each component counter can be programmed, via its PMR register, to be enabled by this bit or by an external EV pin. Reset: Reset all performance monitor registers in this component to default state. This will put every counter in an inactive state and allow programming only the counters of interest. The PERFCON register is not affected by this bit since it can be set to any desired value while setting the Reset control. This bit will automatically be cleared after the reset is completed so a separate programmed operation is not needed to clear it. For diagnostic purposes, the other registers can be read to verify proper operation. Description
0
RW
0
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Configuration Registers
3.41
SP Performance Monitor Response and Control Registers (SP_PMR[1:0])
The PMR registers control operation of their associated counter, and provide overflow or max compare status information.
Device: Node_ID Function: 5 Offset: C0h (SP_PMR[0]), C4h (SP_PMR[1]) Bit 31:26 25 Attr RV RW Default 0 0 Reserved. Req/RspType Bus Select: 0 = Request Bus 1 = Response Bus 24 RW 0 Event Register Select: The PME register select events based on the SP header fields. The SP_PME_RSC register selects resource specific events that are mutually exclusive of the SP header events. One or the other of the event sets can be selected. 0 = SP events 1 = SP resources 23:22 RW 0 Compare Mode: This field defines how the PMCMP register is to be used. 00 - Compare mode disabled (PMCMP register not used). 01 - Max compare only: The PMCMP register value is compared with the counter value. If the counter value is greater then Count Compare Status (bit 13) of the "Event Status" field of this register will be set. 10 - Max compare with update of PMCMP at end of sample: The PMCMP register value is compared with the counter value, and if the counter value is greater, the PMCMP register is updated with the counter value. The Event Status field is not affected in this mode. 11 - Address compare mode where the PMCMP register is compared with the address field. Counter 0 of a counter pair will compare on an address greater than the register, and counter 1 will compare on an address equal to or lesser than the register (inverse of greater than). When both comparisons are valid, an address range comparison qualification is generated. This mode will cause the address range comparison to be AND'ed with the event qualification specified in the selected PME register of each counter. The Event Status field is not affected in this mode. The Address comparison range is A[38:7]. 21:19 RW 0 Reset Event Select: Counter and event status will reset and counting will continue. 000 - No reset condition. 001 - Partner's event status: When the partner counter causes an event status condition to be activated, either by a counter overflow or max comparison, then this counter will reset and continue counting. 010 - Partners PME register event: When the partner counter detects a match condition that meets its selected PME register qualifications, then this counter will reset and continue counting. 011 - Reserved 100 - EV0 pin 101 - EV1 pin 110 - EV2 pin 111 - EV3 pin Description
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Configuration Registers
Device: Node_ID Function: 5 Offset: C0h (SP_PMR[0]), C4h (SP_PMR[1]) (Continued) Bit 18:16 Attr RW Default 0 Count Event Select: This field determines the counter enable source. 000 - PME register event. 001 - Partner event status (max compare or overflow). 010 - All clocks when enabled. 011 - Reserved 100 - EV0 pin 101 - EV1 pin 110 - EV2 pin 111 - EV3 pin 15:14 RW 0 Count Mode: 00 - Count event selected by Count Event Select field. 01 - Count clocks after event selected by Count Event Select field. 10 - Count transaction length of event selected by Count Event Select field. 11 - Reserved 13:12 RW 0 Event Status: This status bit captures an overflow or count compare event. The Event Status Output field can be programmed to allow this bit to be driven to an external EV pin. 00 - No event. x1 - Overflow -The PMD counter overflow status. 1x - Count compare - PMD counter greater than PMCMP register when in compare mode. This bit is sticky in that once an event is reported the status remains even though the original condition is no longer valid. This bit can be cleared by software or by starting a sample. Event status is always visible in the PERFCON register, except if "Event Status Output" field is in cascade mode. Note, if in address compare mode (compare mode = 11), the count compare bit is not activated. 11:9 RW 0 Event Status Output: This field selects where event status is reported, or an address compare if in address compare mode (compare mode = 11). 000 - Event status reported only in PERFCON register. 001 - Event status (overflow) reported to partner only. Used for cascading event counters. 100 - Event status or address comparison in PERFCON and on EV0 pin. 101 - Event status or address comparison in PERFCON and on EV1 pin. 110 - Event status or address comparison in PERFCON and on EV2 pin. 111 - Event status or address comparison in PERFCON and on EV3 pin. Description
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Configuration Registers
Device: Node_ID Function: 5 Offset: C0h (SP_PMR[0]), C4h (SP_PMR[1]) (Continued) Bit 8:5 Attr RW Default 0 Counter Disable Source: These bits control which input disables the counter. Note, if the "Enable Source" is inactive counting is also disabled. 1xxx - EV3 pin x1xx - EV2 pin xx1x - EV1 pin xxx1 - EV0 pin 4:2 RW 0 Counter Enable Source: These bits identify which input enables the counter. Default value disables counting. 000 - Disabled 001 - PERFCON local_count_enable field. 010 - Partner event status (max compare, overflow, or cascade). 011 - Reserved 100 - EV0 pin 101 - EV1 pin 110 - EV2 pin 111 - EV3 pin 1 RW 0 Clear Overflow: This bit clears the overflow bit in associated PMD counter. The counter continues counting. This bit is cleared by hardware when the operation is complete. Reset: Setting this bit resets all registers associated with this counter to the default state. It does not change this PMR register since any desired value can be loaded while setting the Reset bit. This Reset bit will clear itself after the reset is completed. For diagnostic purposes, the contents of the other registers can be read to verify operation of this bit. There is also a reset bit in the PERFCON register that clears all counter registers including the PMR. Description
0
RW
0
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Configuration Registers
3.42
SP Performance Monitor Event Registers (SP_PME[1:0])
The SP performance counter logic provides the ability to monitor packets received by the SP interface of the SIOH. Events related to processor-generated PCI device requests and responses to PCI-initiated memory reads can be monitored. The PME register is divided into major sub-groups. For some sub-groups, the events within a group are OR'ed together.
Device: Node_ID Function: 5 Offset: C8h (SP_PME[0]), CCh (SP_PME[1]) Bit 31:28 27:25 Attr RW RW Default 0 0 DFT Events Mask (OR'ed group) DLEN Field: Encodes the length of the transaction. 111 - Any length 000 - 0-8 bytes 001 - 16 bytes 010 - 32-bytes 011 - 64-bytes 100 - 128-bytes 101 to 110 - Reserved 24:21 RW 0 Attribute: 1111 - All attributes selected. xxxx - Value of the attribute field of the packet used to select (except 1111). 20:16 RW 0h Packet Src Node: 11111 - All sources. xxxxx - Value of the Src Node ID used to select (except 11111). 15:14 RW 00 SP Port Select: 00 - Reserved 01 - SP0 10 - SP1 11 - SP0 or SP1 Packet Type Selection Group 13:7 RW 0 Type_Data: xxxxyyz For request packets, the fields are: * xxxx is the request type major encoding. * yy is the request type minor encoding. * z is the coherency bit. For response packets, the fields are: * xxxx is the response type. * yy indicates the completion bit value (0y). * z is the coherency bit. 6:0 RW 0 Type_Mask: Determines which bits of the Type_Data field to be used in selecting the event. A value of 7Fh (all 1's) selects all packets. Description
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Configuration Registers
3.43
SP Performance Monitor Resource Event Registers (SP_PME_RSC[1:0])
These registers contain resource selections that are mutually exclusive to the event selections. These selections are not qualified by the event selections. Each individual field selection is OR'ed with the other fields to generate the counter match condition. These registers are selected via the Event Register Select Field in the PMR register.
Device: Node_ID Function: 5 Offset: D0h (SP_PME_RSC[0]), D4h (SP_PME_RSC[1]) Bit 31:3 2:0 Attr RW RW Default 0 0 Reserved. Write Cache: 000 - Disable count. 001 - Miss - Inbound write (request for ownership) results in a miss of the write cache. 010 -Inbound Hit Modified (unowned by any IOQ)- An inbound write hits a modified line in the write cache. 011 - Inbound Hit Modified, Stolen (different IOQ steals the line owned by another IOQ)- An inbound write hits a modified line in the write cache. 100 - Inbound Hit Exclusive (different IOQ steals the line)- An inbound write hits an exclusive line in the write cache. 101 - Outbound Invalidate Modified - Results in an implicit writeback. 110 - Outbound Invalidate Exclusive - SIOH gives up ownership of the line to the initiator on the SP. 111 - Line Eviction - Results in an explicit writeback. Description
3.44
SP Performance Monitor Data Registers (SP_PMD[1:0])
These registers are the actual counter value. The overflow bit can be cleared via the PMR register without perturbing the value of the counter. This counter is reset at the beginning of a sample period. The counter can be preloaded to cause an early overflow, otherwise it will be reset at the start of a sample period.
Device: Node_ID Function: 5 Offset: D8h (SP_PMD[0]), DCh (SP_PMD[1]) Bit 31 30:0 Attr RW RW Default 0 0 Overflow. Current counter value. Description
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Configuration Registers
3.45
SP Performance Monitor Compare Register (SP_PMCMP[1:0])
The compare register can be used three ways as selected in the "Compare Mode" field of the PMR register. First, when PMD is incremented, the value of PMD is compared to the value of PMCMP. If PMD is greater than PMCMP, this status is reflected in the PERFCON register and/or on EV pins as selected in the "Event Status Output" field of the PMR register. Secondly, update the PMCMP register with the value of PMD if the PMD register exceeds the contents of PMCMP. The third mode is an address comparison mode. PMD0 compares on addresses greater than the PMCMP0 register, and PMD1 compares on addresses less than or equal to PMCMP1. The "AND" of these two comparisons is the address range comparison and it qualifies the other match event conditions for both counters. Note that the contents of PMCMP are compared to A[38:7].
Device: Node_ID Function: 5 Offset: E0h (SP_PMCMP[0]), E4h (SP_PMCMP[1]) Bit 31:0 Attr RW Default FFFF_FFFFh Counter compare value. Description
3.46
Error Command Registers (ERRCOM)
These registers enable error checking and flagging on various error conditions.
Device: Node_ID Function: 6 Offset: 40h Bit 15 14:10 Attr RV RW Default 0 11111 Reserved. SP Timer Duration: Time-out = 2size cycles, where size is determined by the value of this field. Maximum value is 24 (the timer is a 24-bit counter, incrementing at core clock divided by 8, or 25 MHz). The maximum time-out is approximately 2X the timer duration. If this field is all ones, the SP Timer is disabled. Reserved. Error Freeze on Fatal Error: 0 = Normal operation. 1 = Disable Hub Interfaces and SP interfaces when a fatal error is signaled or observed on the ERR[2:0]# pins. 1 RW 0 Error Freeze Upon Non-Correctable Error: 0 = Normal operation. 1 = Disable Hub Interfaces and SP interfaces when a non-correctable error is signaled or observed on the ERR[2:0]# pins. 0 RW 0 Error Freeze Upon Correctable Error: 0 = Normal operation. 1 = Disable Hub Interfaces and SP interfaces when a correctable error is signaled or observed on the ERR[2:0]# pins. Description
9:3 2
RV RW
0 0
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Configuration Registers
3.47
First Error Status Registers (FERRST)
Errors are classified into two basic types: fatal (or non-recoverable) and non-fatal (or recoverable). Non-fatal errors are further classified into correctable and non-correctable errors. First fatal and/or non-fatal errors are flagged in the FERRST register. At most two errors can be reported by the FERRST; one for non-recoverable (or fatal) errors, one for recoverable (or uncorrectable and correctable) errors. Associated with some of the errors flagged in the FERRST register are control and data logs. In some cases, the logs are duplicated for the same error. Fields in the FERRST register identify which unit has the corresponding error. Once a first error for a type of error has been flagged (and logged), the log registers for that error type remain fixed until either the bit associated with the error type in the FERRST is cleared, or a power-on reset. Contents of the error logs are not reliable unless an error associated with the log is reported in FERRST. When the first error of a type is detected (fatal, uncorrectable, correctable), the value of the error status pin associated with this error type is latched in the FERRST register.
Device: Node_ID Function: 6 Offset: 44h Bit 63 Attr ROS Default Last State of ERR[2]# (inverted) State of last ERR[1]# (inverted) ERR Type N/A Description Last Fatal Error State: The value on the ERR[2]# pin input (inverted for active high indication) is captured here immediately when a fatal error is latched in the FERRST. This allows software to identify the component that drove the first fatal error when the ERR[2:0]# pins are wired-or together with the other components. Last Uncorrectable Error State: The value on the ERR[1]# pin input (inverted for active high indication) is captured here immediately when an Uncorrectable error is latched in the FERRST. This allows software to identify the component that drove the first uncorrectable error when the ERR[2:0]# pins are wired-or together with the other components. Last Correctable Error State: The value on the ERR[0]# pin input (inverted for active high indication) is captured here immediately when a correctable error is latched in the FERRST. This allows software to identify the component that drove the first correctable error when the ERR[2:0]# pins are wired-or together with the other components. Reserved.
62
ROS
N/A
61
ROS
State of last ERR[0]# (inverted)
N/A
60:57
RV
0
N/A
Start of SPP Error Bits 56 55 54 53 RCS RCS RCS RCS 0 0 0 0 Fatal Fatal Fatal Fatal SP Protocol Error: Set when the SP protocol state machines wind up in an indeterminate state, or for protocol errors. SP Queue/Buffer (LRB) Time-out Error: Refer to the ERRCOM register. Received Failed or Unexpected Unsupported Response: Set if a Failed or Unexpected unsupported response is received on the SP. Strayed SP Transaction: Set when strayed transactions are detected on SP cluster. A "strayed" transaction is one where a completion returns for a transaction that was never requested. Reserved.
52
RV
0
N/A
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Configuration Registers
Device: Node_ID Function: 6 Offset: 44h (Continued) Bit 51 Attr RCS Default 0 ERR Type Unc Description Partial Merge Multi-Bit Data ECC Error: A partial write occurs to the write cache (requiring a RMW) and a multi-bit ECC error is detected on the data. ECC checking, correction and/or poisoning is done within the 8-byte boundary of the partial write. Partial Merge Single-Bit Data ECC Error: A partial write occurs to the write cache (requiring a RMW) and a multi-bit ECC error is detected on the data. ECC checking, correction and/or poisoning is done within the 8-byte boundary of the partial write. Illegal SP Address Error: Set when an illegal address is detected on the SP. This includes an inbound access when: * Both SP ports are disabled. * An inbound access targeting an inoperative SP port (unframed). * Outbound SP requests with illegal attributes. * Outbound addresses that miss all the SIOH address range registers. 48 RCS 0 Corr Received Master Abort Response: Set if a master abort response is received on the SP.
50
RCS
0
Corr
49
RCS
0
Corr
Start of Hub Interface Error Bits 47:45 ROS 000 N/A Hub Interface Fatal Error Pointer: If a Hub Interface cluster has reported the first fatal error, this field indicates which cluster has reported the error. 000 - Hub Interface Port 0 001 - Hub Interface Port 1 010 - Hub Interface Port 2 011 - Hub Interface Port 3 100 - Hub Interface Port 4 101 to 111 - Reserved 44:42 ROS 0 N/A Hub Interface Uncorrectable Error Pointer: If a Hub Interface cluster has reported the first non-fatal error and the error is uncorrectable, this field indicates which cluster has reported the error. 000 - Hub Interface Port 0 001 - Hub Interface Port 1 010 - Hub Interface Port 2 011 - Hub Interface Port 3 100 - Hub Interface Port 4 101 to 111 - Reserved 41:39 ROS 0 N/A Hub Interface Correctable Error Pointer: If a Hub Interface cluster has reported the first non-fatal error and the error is correctable, this field indicates which cluster has reported the error. 000 - Hub Interface Port 0 001 - Hub Interface Port 1 010 - Hub Interface Port 2 011 - Hub Interface Port 3 100 - Hub Interface Port 4 101 to 111 - Reserved 38 RCS 0 Fatal Hub Interface Header Multi-Bit ECC Error (Hub Interface 2.0) or Parity Error (Compatibility Port): Set if a multi-bit ECC error (Hub Interface 2.0)or parity error (Hub Interface 1.5) is detected in the header of a Hub Interface packet.
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Configuration Registers
Device: Node_ID Function: 6 Offset: 44h (Continued) Bit 37 36 Attr RCS RCS Default 0 0 ERR Type Fatal Fatal Description Hub Interface - Received DO_SERR# Message: The SIOH received a DO_SERR# special cycle on the Hub Interface. Received Illegal Hub Interface Request, Unexpected or Invalid Response: The SIOH received an unsupported transaction: * Inbound I/O read or write transaction. * Inbound Configuration read or write transaction. * Inbound Unsupported Special cycle. * Inbound Locked read or write transactions. * Any inbound write with a completion required. * Any outbound completion that does not match with any pending outbound request. 35 34 33 RV RCS RCS 0 0 0 Unc Unc Reserved. Received Hub Interface Target Abort: A Hub Interface outbound read or delayed write receives a Target Abort completion. Inbound Hub Interface Multi-Bit Data ECC Error (Hub Interface 2.0) or Parity Error (Compatibility Port): Set if a multi-bit ECC error (Hub Interface 2.0) or parity error (Hub Interface 1.5) is detected in the data of a Hub Interface packet. This bit applies to data flowing inbound (inbound write and outbound read completion). Outbound Multi-Bit Data ECC Error at Hub Interface 1.5 Cluster: Before forwarding a packet on Hub Interface 1.5 (SIOH end points), the Hub Interface cluster detects a multi-bit ECC error on the data. This bit applies to data flowing outbound (outbound write and inbound read completion). Reserved. Corr Inbound Hub Interface 2.0 Single-Bit Data ECC Error: Set if a single-bit ECC error is detected in the data of a Hub Interface packet. This bit applies to data flowing inbound (inbound write and outbound read completion). Received Hub Interface 2.0 Header Single-Bit ECC Error: Set if a single-bit ECC error is detected in the header of a Hub Interface packet. Outbound Single-Bit Data ECC Error at Hub Interface 1.5Cluster: Before forwarding an outbound write or inbound read completion packet on Hub Interface 1.5 (SIOH end points), the Hub Interface cluster detects a single bit ECC error on the data. Hub Interface Illegal Address Error: Set when an inbound illegal address is detected at the Hub Interface interface. Received Master Abort on Hub Interface or unimplemented special cycle: This bit is asserted when the SIOH receives a master abort termination on the bus for an outbound transaction, or a special cycle that is not implemented by the interfacing component. Reserved.
32
RCS
0
Unc
31 30
RV RCS
0 0
29
RCS
0
Corr
28
RCS
0
Corr
27 26
RCS RCS
0 0
Corr Corr
25:18
RV
0
N/A
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Configuration Registers
Device: Node_ID Function: 6 Offset: 44h (Continued) Bit Attr Default ERR Type Description
Start of SPL Error Bits 17:15 14 RV ROS 0 0 N/A Reserved. SPL Fatal Error Pointer: If an SPL has reported the first fatal error, this field indicates which SP has reported the error. 0 = SP 0 1 = SP 1 13 ROS 0 N/A SPL Uncorrectable Error Pointer: If an SPL has reported the first non-fatal error and the error is an uncorrectable error, this field indicates which SP has reported the error. SPL Correctable Error Pointer: If an SPL has reported the first non-fatal error and the error is a correctable error, this field indicates which SP has reported the error. Link Error: Failed SP LLR, LLR not enabled, or strobe glitch error. SP Multi-Bit Data ECC Error. Idle Flit Duplication Error. Parity Error on the Link. SP Single-Bit Data ECC Error.
12
ROS
0
N/A
11 10 9 8 7
RCS RCS RCS RCS RCS
0 0 0 0 0
Fatal Unc Corr Corr Corr
Start of Configuration Error Bits 6:2 1 RV RCS 0h 0 Fatal Reserved. Configuration Multi-Bit Data ECC Error: This bit is set when a multi-bit ECC error was detected on data written to the SIOH configuration registers. Configuration Single-Bit Data ECC Error: This bit is set when a single-bit ECC error was detected on data written to the SIOH configuration registers.
0
RCS
0
Corr
Refer to Table 3-6 for the logging registers used with each group. Table 3-6. Error Log Register Grouping
Error Bit Group SPP Hub Interface SPL Configuration Logging Registers RECSPP, NRECSPP RECHUB, REDHUB, NRECHUB, PCISTS RECSPL[1:0], REDSPL[1:0] RECSPP
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Configuration Registers
3.48
Two or More Errors Status Register (SERRST)
This register indicates that two or more instances of errors have happened in the SIOH. Multiple bits can be set in this register. Each bit in this register (except FERRST[63:61]) corresponds to the same bit descriptions in the FERRST register. Note: Multiple error occurrences cause the pointer fields of this register (SERRST[14:12] and SERRST[47:39]) to be invalid.
Device: Node_ID Function: 6 Offset: 4Ch Bit 63:57 56:0 Attr RV Default 0 ERR Type N/A Reserved. Description
See the FERRST register for the definition, attribute and default state of each bit.
3.49
Error Mask Registers (ERRMASK)
The size of this register exactly matches the size of FERRST register. Each bit in this register will mask the corresponding bit in FERRST and SERRST. "Mask" here means that while the corresponding bit in FERRST or SERRST register can still be set or cleared, it won't trigger events on ERR[2:0]#.
Device: Node_ID Function: 6 Offset: 54h Bit 63:57 56:0 Attr RV RW Default 0 All 1's Reserved. 0 = No effect. 1 = Mask the corresponding bit in the FERRST and SERRST registers. Description
3.50
SPP Recoverable Error Control Register (RECSPP)
This register latches control information for the first non-fatal error detected inside the SP cluster. Not all errors have logs.
Device: Node_ID Function: 6 Offset: 64h Bit 63:0 Attr ROS Default 0 Description SP request/response header or internal request/response header.
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Configuration Registers
3.51
SPP Non-Recoverable Error Control Register (NRECSPP)
This register latches control information for the first fatal error detected inside the SPP cluster. Not all errors have logs.
Device: Node_ID Function: 6 Offset: 78H Bit 63:0 Attr ROS Default 0 Description SP request/response header or internal request/response header.
3.52
SP Interface Control Registers (SPINCO[1:0])
These registers are common across all E8870 chipset components, and they provide the control and status for each SP. Two GPIO pins (GPIO[1:0]) are associated with each SP. These pins are open drain, and are observable and controllable from this register.
Device: Node_ID Function: 6 Offset: 80h (SPINCO[0]), A0h (SPINCO[1]) Bit 31:26 25 Attr RWS RO Default 0 GPIO[1] state Description Scratch Bits: These bits may be used by software to record information specific to this SP. For example, hot-plug sequencing history. GPIO[1] State: This bit reflects the state of GPIO[1]. 0 = GPIO[1] pin is high. 1 = GPIO[1] pin is low. 24 RO GPIO[0] state 0 GPIO[0] State: This bit reflects the state of GPIO[0]. 0 = GPIO[0] pin is high. 1 = GPIO[0] pin is low. 23 RWS GPIO[1] Output Enable: This bit configures GPIO[1] as an input or output signal. 0 = Do not drive the GPIO[1] pin (input only). 1 = Drive the GPIO[1] pin low (open drain output). 22 RWS 0 GPIO[0] Output Enable: This bit configures GPIO[0] as an input or output signal. 0 = Do not drive the GPIO[0] pin (input only). 1 = Drive the GPIO[0] pin low (open drain output). 21 RW 0 INT_OUT: 0 = Do not drive the INT_OUT# pin low. 1 = Drive the INT_OUT# pin low (open drain output). 20:19 RO 0 SPAlign: The value of this field reflects the staging delays through the scalability port input mux to frame the transfer of data from the SP source synchronous data transfer to the core clock of the component. Response Credits: Credits supported by this SP port on the response VC. Credit = 2size except that when size >= 101, credit = 25 instead of 32. These bits are sent in the idle flits. Must be set to a value <= 25 for reliable SP operation.
18:16
RWS
101
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Configuration Registers
Device: Node_ID Function: 6 Offset: 80h (SPINCO[0]), A0h (SPINCO[1]) (Continued) Bit 15:13 Attr RWS Default 101 Description Request Credits: Credit supported by this SP port on request VC. Credit = 2size except that when size >= 5 (101b), credit = 25 instead of 32. These bits are sent in the idle flits. Must be set to a value <= 25 for reliable SP operation. Disable SP Link Level Retry (LLR): When set, this bit will disable link level retry on SP. Note: SP LLR is always disabled during framing/initialization. Connecting SP Response Credits: Credits supported by the response VC of the device connected to this SP port. Credit = 2size except that when size= 5 (101b), credit = 25 instead of 32. This field is captured and updated from the idle flits. Connecting SP Request Credits: Credits supported by the request VC of the device connected to this SP port. Credit = 2size except that when size = 5 (101b), credit = 25 instead of 32. This field is captured and updated from the idle flits. Enable SP: 0 = The port is disabled. The outputs of the SP excluding SPSync are tri-stated. Deassertion will cause the port to deassert SPSync and enter initialization sequence. Disabling an SP should not be done with a configuration transaction from the same SP as the one being disabled. The configuration write will not complete. 1 = Enable SP output drivers. The port must complete initialization and framing before data can be transferred. 4 RO 0 Idle Flit Acknowledgment Detected: Detected idle_ack from the idle flits received by this SP. This bit is cleared at the beginning of the initialization sequence. Idle Flit Detected: Set during framing when 256 valid idle flits in a row are detected by the SP receiver. This bit is cleared at the beginning of the initialization sequence. Interrupt on SP Idle Flit State Change: 1 = A 0->1 transition of the idle-flit-detected bit in the above field will trigger an interrupt from this chip via INT_OUT#. 0 = De-assert the interrupt request controlled by this bit. The open drain interrupt pin (INT_OUT#) may remain asserted if other interrupt conditions exist. Note that the detection mechanism is initialized at the start of port framing only. 1 RO See SP_PRES State: This bit follows the SP_PRES pin associated with this SP. Description When deasserted, the output of the SP are tri-stated, and transactions targeting the SP are master-aborted. 0 Interrupt on Pin SP_PRES State Change: 1 = A 0->1 or 1->0 transition in the above field will trigger an interrupt from this chip (via INT_OUT#). 0 = De-assert the interrupt request controlled by this bit. The open drain interrupt pin (INT_OUT#) may remain asserted if other interrupt conditions exist.
12 11:9
RW RO
0 0
8:6
RO
0
5
RWS
1
3
RO
0
2
RW
0
0
RW
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Configuration Registers
3.53
SPL Recoverable Error Control Register (RECSPL[1:0])
This register latches control information for the first non-fatal error detected inside the SPL cluster. Not all errors have logs.
Device: Node_ID Function: 6 Offset: 84h (RECSPL[0]), A4h (RECSPL[1]) Bit 63:0 Attr ROS Default 0 Description SP request/response header or SP PHIT#, PHIT parity and PHIT, SP LLR retry counts.
3.54
SPL Recoverable Error Data Registers (REDSPL[1:0])
These registers latch Syndrome and ECC information for the first non-fatal error detected inside the SPL cluster. Not all errors have logs.
Device: Node_ID Function: 6 Offset: 84h (REDSPL[0]), A4h (REDSPL[1]) Bit 15:8 7:0 Attr ROS ROS Default 00h 00h Description Syndrome: This field is the calculated syndrome. This field points to the error type (multi or single-bit) and the data bit in error for single-bit errors. ECC: This field is the ECC packet received on the SP for the flit in error.
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Configuration Registers
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Address Map
4.1 Address Ranges
4
Relatively few memory spaces are positively decoded by the SIOH. Any inbound address that falls outside the regions described in this chapter is routed to the SP interface.
4.1.1
Memory-Mapped I/O
Figure 4-1 shows the memory-mapped I/O map as seen by the SIOH component. There are two MMIO regions for the SIOH. One region is programmed to a window below 4 GB with MMIOBL, MMIOLL, and MMIOSL[5:0] while the other is programmed above 4 GB with MMIOBH, MMIOLH, and MMIOSH[5:0]. The registers defining each of these regions are described in Chapter 3, "Configuration Registers". These registers restrict the low MMIO granularity to 16 MB and the high MMIO granularity to 64 MB. The purpose for two regions is to support the added requirement of PCI-X, which inherently supports addressing above 4 GB (greater than 32-bit). Applications such as clustering require large MMIO spaces so that one server has a window into the other server's memory space. Note: Figure 4-1 illustrates an image when there is no memory-mapped I/O space associated with Hub Interface Port 1. In addition, since the ICH4 cannot support MMIO space greater than 32-bits, Port 0 will not be programmed to have a high MMIO range. For E8870 chipset-based platforms, the MMIOLL register will be programmed to an upper limit of FDFF_FFFFh. For ease of BIOS PCI enumeration, the compatibility bus MMIO space is at the top. BIOS sets up the MMIO space for the compatibility bus (bus 0) first. If this space was not at the top, it would need to be first programmed to the top and continually reprogrammed (moved down) throughout the enumeration process. When the platform supports two SIOH components, MMIOBL, MMIOBH, MMIOLL, and MMIOLH must be programmed identically in both SIOH components. For proper peer-to-peer operation, the MMIOS registers of the second SIOH component must be programmed within MMIOB{H/L} and MMIOL{H/L}. Note: In order to allow an SIOH to manage a contiguous MMIO space, the base (MMIOB{H/L}) or limit register (MMIOL{H/L}) must be programmed to the same value as either MMIOS{H/L}[0] or MMIOS{H/L}[5]. Figure 4-1 illustrates a correct programming example. Programming the base and limit registers outside of the aperture defined by the contiguous segment registers is an invalid programming model.
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Address Map
Figure 4-1. SIOH Memory-Mapped I/O Space Example
M M IO LH
A llocated for O ther SIOH
M MIOS H[0], M MIOS H[1], M MIOS H[2]
Hub Interface 2
M M IO SH[3] Hub Interface 3 MM IOS H[4] Hub Interface 4 M M IO BH, M M IOS H[5] 4 G byte Boundary
M M IO LL, MM IOS L[0] Hub Interface 0 M M IOS L[1], M M IOS L[2] Hub Interface 2 M MIOS L[3] Hub Interface 3 M MIOS L[4] Hub Interface 4 M M IO SL[5]
A llocated for O ther SIOH M M IO B L
001126a
To determine where to forward a memory-mapped I/O cycle, refer to Table 4-1. Table 4-1. Memory-Mapped I/O Cycle Routing
Forward to SPS (inbound only) Address Comparison MMIOLH >= Address[41:26] > MMIOSH[0] (Address[63:42] = 0) MMIOSH[5] >= Address[41:26] > MMIOBH (Address[63:42] = 0) MMIOLL >= Address[31:24] > MMIOSL[0] (Address[63:32] = 0) MMIOSL[5] >= Address[31:24] > MMIOBL (Address[63:32] = 0) Hub Interface Port 0 MMIOSH[0] >= Address[41:26] > MMIOSH[1] (Address[43:42] = 0) MMIOSL[0] >= Address[31:24] > MMIOSL[1] (Address[43:32] = 0) Hub Interface Port 1 MMIOSH[1] >= Address[41:26] > MMIOSH[2] (Address[43:42] = 0) MMIOSL[1] >= Address[31:24] > MMIOSL[2] (Address[43:32] = 0)
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Address Map
Table 4-1. Memory-Mapped I/O Cycle Routing (Continued)
Forward to Hub Interface Port 2 Address Comparison MMIOSH[2] >= Address[41:26] > MMIOSH[3] (Address[43:42] = 0) MMIOSL[2] >= Address[31:24] > MMIOSL[3] (Address[43:32] = 0) Hub Interface Port 3 MMIOSH[3] >= Address[41:26] > MMIOSH[4] (Address[43:42] = 0) MMIOSL[3] >= Address[31:24] > MMIOSL[4] (Address[43:32] = 0) Hub Interface Port 4 MMIOSH[4] >= Address[41:26] > MMIOSH[5] (Address[43:42] = 0) MMIOSL[4] >= Address[31:24] > MMIOSL[5] (Address[43:32] = 0)
For example, assume that MMIOSL[0] is programmed to FD and MMIOSL[1] is programmed to F9. This programming indicates that Hub Interface Port 0 claims the range from FA00_0000h to FDFF_FFFFh. To disable an MMIO range, the base and limit registers for that segment are programmed to the same value. For example, to disable Hub Interface Port 2, program MMIOSH[2] and MMIOSH[3] to the same value and MMIOSL[2] and MMIOSL[3] to the same value.
4.1.2
I/O Space
Figure 4-2 shows the I/O memory map seen by the SIOH. There is a total of 64 KB of legacy I/O space for the system. The SIOH component must be programmed so that I/O spaces do not overlap. Note: Figure 4-2 illustrates the image when there is no I/O space associated with Hub Interface Port 3. Refer to Table 4-2 to determine where to forward an I/O cycle based on the I/O address. If the SIOH receives an I/O transaction where the address does not fall within any of the I/O spaces and the attribute is set to DND, then the transaction should be master aborted.
Figure 4-2. SIOH I/O Space
FFFFh
Allocated for Other SIOH
IOL[5] Hub Interface 4 IOL[3], IOL[4] Hub Interface 2 IOL[2] Hub Interface 1 IOL[1] Hub Interface 0 (Compatibility Bus) 0000h IOL[0]
001127a
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Address Map
Table 4-2. I/O Cycle Routing
Forward to Hub Interface Port 0 Hub Interface Port 1 Hub Interface Port 2 Hub Interface Port 3 Hub Interface Port 4 Address Comparison IOL[0] <= Address[15:11] < IOL[1] IOL[1] <= Address[15:11] < IOL[2] IOL[2] <= Address[15:11] < IOL[3] IOL[3] <= Address[15:11] < IOL[4] IOL[4] <= Address[15:11] < IOL[5]
Note:
The IOL registers have one bit more than the address bits they compare with (15:11). This is necessary since the upper boundary (IOL[5] for example) actually points to one block above the port it indicates. The compatibility port is required to have a 4 KB region allocated to it. The highest dedicated I/O address required for legacy is 0CF9 (reset generator) and therefore exceeds the 2 KB granularity of the SIOH.
4.1.2.1
I/O Space Programming Example
Assume that a single SIOH consumes the entire I/O space (0000 - FFFFh). Table 4-3 lists an example of I/O space partitioning and how the IOL registers would be programmed. In terms of comparison, IOL[5:0] is compared with I/O address[16:11], even though for I/O addresses, A[16] doesn't exist.
Table 4-3. I/O Space Programming Example
Hub Interface 0 1 2 3 4 I/O Region 0000 - 3FFFh 4000 - BFFFh C000 - D7FFh D800 - EFFFh F000 - FFFFh IOL Programming IOL[0] = 00h IOL[1] = 08h IOL[2] = 18h IOL[3] = 1Bh IOL[4] = 1Eh IOL[5] = 20h
4.1.3
SAPIC/IOAPIC and PCI Hot-Plug Ranges
There are five SAPIC/IOAPIC/PCI Hot-Plug ranges (SAR ranges) programmed for the SIOH. Each Hub Interface port correlates with one range implying that the P64H2's two SAPIC and PCI Hot-Plug controllers (one per PCI-X bus) must reside within the same contiguous region. Refer to Table 4-4 to determine where to forward SAR transactions. Note: System software must ensure that both the SAPIC and Hot-Plug ranges for the PCI bridge are within the same region.
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Address Map
Figure 4-3. SIOH SAPIC Space
FECF_FFFFh
Allocated for other SIOH
SSEG[5] Hub Interface 4 SSEG[3], SSEG[4] Hub Interface 2 SSEG[2] Hub Interface 1 SSEG[1] Hub Interface 0 (Compatibility Bus) FEC0_0000h SSEG[0]
001128a
Table 4-4. SAPIC/IOAPIC and PCI Hot-Plug Cycle Routing
Forward to SPS (inbound only) Address[19:8] < SSEG[0] SSEG[5] <= Address[19:8] Hub Interface Port 0 Hub Interface Port 1 Hub Interface Port 2 Hub Interface Port 3 Hub Interface Port 4 SSEG[0] <= Address[19:8] < SSEG[1] SSEG[1] <= Address[19:8] < SSEG[2] SSEG[2] <= Address[19:8] < SSEG[3] SSEG[3] <= Address[19:8] < SSEG[4] SSEG[4] <= Address[19:8] < SSEG[5] Address Comparison1
1. Address[43:20] must match 000FECh.
For example, assume that SSEG[0] is programmed to 000h, and SSEG[1] is programmed to 100h. This programming indicates that Hub Interface Port 0 claims the range from FEC0_0000h to FEC0_FFFFh. To disable a range, the base and limit registers for that segment are programmed to the same value. For example, to disable Hub Interface Port 2, program SSEG[2] and SSEG[3] to the same value. Note: The SSEG registers have one bit more than the address bits they compare with (19:8). This is necessary since the upper boundary (SSEG[5] for example) actually points to one block above the port it indicates.
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Address Map
4.1.4
Compatibility Bus
The IOCTL register defines if the compatibility bus interfaces this SIOH component. The compatibility bus is defined as the Hub Interface port interfacing the ICH4 component and is always Hub Interface Port 0 throughout this document. (Refer to Section 3.25, "SIOH Control Registers (IOCTL)" for details.)
4.1.5
VGA Space
The IOCTL register defines the Hub Interface port that connects to the bridge interfacing the video adapter. The SIOH uses this register as a pointer to send accesses to the legacy VGA space. This register allows the VGA adapter to reside on any Hub Interface port. (Refer to Section 3.25, "SIOH Control Registers (IOCTL)" for details.)
4.1.5.1
MDA Space
The IOCTL register defines a bit that enables the legacy Monochrome Display Adapter space on the compatibility bus. This legacy MMIO space comprises 000B_0000h to 000B_7FFFh. If enabled, all inbound MDA accesses are routed to the compatibility port. This routing allows a monochrome adapter to reside on the compatibility bus whereas the VGA adapter might reside wherever the IOCTL indicates. If the bit is disabled, accesses to this range are sent to the VGA port.
4.2
Illegal Addresses
For most illegal accesses, the transaction is master aborted. Master Abort has different specifics depending on the initiating interface.
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Clocking
5.1 SIOH Clocking
5
This chapter describes the external clocking required for the SIOH. Figure 5-1 illustrates an example of how the SIOH receives and provides clocks between other E8870 chipset components. Figure 5-1. SIOH Platform Clocking Example
E xternal Delay
S YSC LK
P CICLK ICH 4
SY SCLK x4
C LK 33
HCLK HLCLK E xternal Clock Buffer HLCLK HLCLK HLC LK P64H2 P64H 2 P 64H2 P 64H2
SIOH
CLK66
FBCLK 66
Delay M atching Required between All Clock B uffer Outputs
001137
5.2
Reference Clock (SYSCLK)
In all E8870 chipset-based systems, a 200 MHz system clock is provided to the SIOH. This clock has no required phase relationship with respect to the SNC clock. This is possible because there are no common clock signals across the SP. This is the reference clock for all SIOH PLLs. The SIOH has multiple external interfaces: SP, 8-bit Hub Interface and 16-bit Hub Interface. The Hub Interfaces have a base frequency of 66 MHz. These interfaces have common clock signals and require an in-phase clock at both sides of the interface. In addition, the 8-bit Hub Interfaces require clocks for quad-pumping the source-synchronous data and 16-bit Hub Interfaces require octal-pumping of the source-synchronous data. The SIOH supplies external Hub Interface components with a 66 MHz clock. To minimize cascaded jitter effects, the E8870 chipset requires a 200 MHz system clock be provided to the P64H2 components.
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Clocking
5.3
Clock Outputs
For the downstream Hub Interface components, the SIOH provides external 66 MHz and 33 MHz clock outputs, with the 66 MHz clock in phase with the reference clock, and the 33 MHz delayed from the 66 MHz output by 1 to 3.5 ns. The SIOH also provides 266 MHz and 533 MHz source-synchronous clock outputs that are in-phase with the reference. The 33 MHz external clock is the only clock signal NOT guaranteed to rise when the synchronization signal indicates rising edge alignment, due to its lower frequency.
5.4
Feedback and Matching
The external 66 MHz clock output also serves as a feedback path to the PLL in the external Hub Interface clock unit. The path from the pad of the external clock and the feedback off of the external clock tree to the clock unit must be matched. The delay of all output legs should be matched. This will put all external devices in-phase with the reference clock and the Hub Interface internal clocks. The external feedback must be matched to the distribution to the P64H2s and ICH4. Mismatches will degrade or break I/O timings.
5.5
JTAG Test Access Port
Logic circuits exist in the JTAG unit to accommodate metastability and synchronization of TCK to SIOH core clocks for private instructions. Two synchronizers are used to provide rising and falling edge detection of the JTAG clock.
5.6
SMBus Clocking
Logic circuits exist in the SIOH to accommodate metastability and synchronization of the serial clock line (SCL) and the serial data line (SDA) to the SIOH core clocks for processing serial data streams. Also included is a 4-bit counter to suppress glitches less than 60 ns in width.
5.7
Spread Spectrum Support
Spread Spectrum Clocking (SSC) is a frequency modulation technique for EMI reduction. Instead of maintaining a constant frequency, SSC modulates the clock frequency/period along a predetermined path (i.e. the modulation profile), with a predetermined modulation frequency. The chipset supports SSC. The modulation will be done with a frequency modulation of 30 kHz with a downspread of 0.5%.
5.8
No Stop Clock or Thermal Shutdown
Clocks in the SIOH can not be stopped. There are no power reduction features in the SIOH. However, the E8870 chipset does support power reduction features through other components such as the processor and ICH4.
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Clocking
5.9
Deterministic Systems
In any SIOH system, the core clock and all SP clocks will be deterministic by default, since they are generated off of the 200 MHz system clock and their frequencies are either equal to that 200 MHz, or a multiple of it. The external CLK33 is CLK66 divided by two. The divider is non-deterministic, so this clock could be non-deterministic as well. It is pointless to clear this divider at the determinism synch-point, since CLK66 will subsequently lose lock, and the 33 MHz phase will not be deterministic when lock is regained. The phase of this signal can still be made deterministic by creating a reference pulse every sixth 200 MHz clock. After the synchronizing event, this pulse occurs at the same time as every other pulse used to qualify 200 MHz edges for comparison with CLK66. If the 33 MHz clock is ever high on the rising edge of the 200 MHz core clock qualified by the divide-by-6, the 33 MHz clock will be inverted, thus generating a deterministic CLK33. To ensure the proper operation of this scheme, the external trace delay of CLK66 (also CLK33) must be no longer than 8 ns from the point where it leaves the SIOH to its point of delivery. The above synchronization is not performed if the DET pin is strapped low.
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Clocking
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Reset
6.1 Reset Sequence Overview
6
The following sections describe the power-up and reset sequences illustrated in Figure 6-1. The timing parameters are listed in Table 6-1. Figure 6-1. SIOH Reset Sequence
PWRGOOD (PWROK on ICH4) RESETI# Hub Interface PLL Locked RESET66# (to ICH4) Hub Interface (ICH4 Initialization Handshake)
RCOMP
T1
T5
T2
T6
NOP Request NOP Compl
CPU_RST_DONE
CPU_RST_DONE Compl
First Normal Transation
T3
T4
T7
T8
T9
T10 T11
001153a
Table 6-1. Power-Up and Hard Reset Timings
Description T1 T2 T3 PWRGOOD assertion to RESETI# deassertion. RESETI# deassertion to Hub Interface PLL locked. First RESETI# deassertion to start of initial Hub Interface RCOMP. Min 1 0 1024 Max 2 1000 Unit ms SYSCLK SYSCLK Comments PWRGOOD is asserted by the system. Applies only to first RESETI# deassertion when DET is asserted. A 10-bit counter from PWRGOOD initiates the first RCOMP. Subsequent resets will not affect the periodic RCOMP and this initial RCOMP is not generated.
T4 T5 T6
Hub Interface RCOMP sequence. RESETI# complete to RESET66# deassertion. RESET66# deassertion to NOP request. NOP request to NOP completion. NOP completion to CPU_RST_DONE request. CPU_RST_DONE request to CPU_RST_DONE completion. CPU_RST_DONE completion to first valid outbound transaction. CPU_RST_DONE completion to first valid inbound transaction.
0 4002 16
T5-T3 4007 20
SYSCLK SYSCLK CLK66 Hub Interface 2.0 requires a minimum of 16 clocks. For the ICH4 there is no requirement. ICH4 specification. When NOP returns, HLCTL[8] set. No ICH4 requirement. ICH4 specification. No ICH4 requirement. SIOH requirement.
T7 T8 T9 T10 T11
0 0 0 0 16
32 10 32 N/A N/A
CLK66 CLK66 CLK66 CLK66 CLK66
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Reset
6.2
Power-Up Sequence
When the SIOH sees PWRGOOD asserted, it begins a power-up sequence. PWRGOOD is typically initiated by system power supplies or local DC/DC converter circuits. PWRGOOD resets all system components to a known reset state (except for some battery back-up circuits). PWRGOOD clears all sticky bits.
6.2.1
PWRGOOD Deasserted
The SIOH asserts RESET66# asynchronously. Internal clocks will not be within specifications while PWRGOOD is deasserted and, therefore, must be treated as asynchronous. All E8870 chipset components will reset any core logic that can be asynchronously reset, and all logic must be forced into a non-destructive state. For example, multiple drivers must not attempt to drive the same signal to different logic values. JTAG chains and any logic clocked by TCK should be cleared. The TAP will not be operational until PWRGOOD is asserted. TCK may or may not be active at this time. All outputs (except for any reset outputs) are placed in a high impedance state.
6.2.2
PWRGOOD Assertion
RESETI# must be asserted by the system for 1 ms after PWRGOOD rises to allow E8870 chipset PLLs to lock. All logic in E8870 chipset components may be reset while RESETI# is asserted the first time after PWRGOOD. Fuse bits are sensed and parallel loaded during PWRGOOD assertion. Fuse bit download that requires sequential operation is not performed at this point as internal clocks are not stable. Clocks stabilize at some point before RESETI# rises, so the parallel loaded fuse information is valid by the time RESETI# rises. Public JTAG chains and any logic clocked by TCK must be operational (even though RESETI# is still asserted). Private JTAG chains need not be operational while RESETI# is asserted. All logic reset by PWRGOOD may be held in reset until Hard Reset Deassertion.The SIOH drives RESET66# asynchronously to CLK66 to reset Hub Interface devices.
6.2.3
First RESETI# Deassertion
The SIOH continues to assert RESET66# (see Figure 6-1). The SIOH resets all clocks lower than 200 MHz on the synchronization point created by first RESETI# deassertion. Sticky configuration bits are cleared, and a Hard Reset Deassertion sequence is started to initialize all SIOH states (see Section 6.3.2, "Hard Reset Deassertion" ). When RESETI# is deasserted, reset straps (e.g. NodeID and BusID) are sampled and latched.
6.3
Hard Reset
Hard Reset is triggered by setting the SIOH reset bit in the SYRE register or RESETI# assertions. For resets initiated with the SIOH SYRE register, Hard Reset of the SIOH is delayed until T5 after SYRE[0] is set. This allows the configuration write to the SYRE register to complete back to the initiator before the SIOH state machines are reset.
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Reset
The SIOH behaves the same for all types of Hard Reset. (There is no difference in the SIOH response to a Local or Domain Hard Reset.) Since a Hard Reset Assertion response and a Hard Reset Deassertion response always occur together in the SIOH, they may be combined into a single flow.
6.3.1
Hard Reset Assertion
All logic reset by PWRGOOD may be held in reset between Hard Reset Assertion and Hard Reset Deassertion. Sticky configuration bits are not cleared. RESET66# is driven by the SIOH synchronous to CLK66 to reset Hub Interface devices.
6.3.2
Hard Reset Deassertion
After RESET66# deasserts synchronous to CLK66, the SIOH begins a CPU_RESET_DONE handshake with the ICH4: 1. SIOH is done with reset (deassertion of RESET66# and PWRGOOD). 2. Send a NOP transaction down the ICH4 Hub Interface. If no completion is received for the NOP transaction (normal or unsupported special cycle), HLCTL[8] is not set and any subsequent transactions targeting the Hub Interface will be master-aborted. 3. If a completion is received for the NOP transaction, issue a CPU_RST_DONE special cycle to the ICH4. 4. After the SIOH receives the CPU_RST_DONE completion (normal or Unsupported Special Cycle) the SIOH remains idle and begins normal operation. HLCTL[8] for function 0 is set, indicating a present Hub Interface component. While the SIOH reset sequence is being performed the SIOH cannot issue other transactions to the ICH4. For a waveform illustrating the above sequence, refer to Figure 6-1. All other logical outputs of the SIOH should be deterministic from Hard Reset. That is, all storage elements in IOs, PLLs, and synchronous logic (except for sticky configuration bits) should be cleared by Hard Reset. During the Hard Reset sequence, any logic feeding into sticky configuration bits should not change the state of those bits. Hard Reset Deassertion also invalidates all the read caches, the write cache, LRB, RRB, and all queues throughout the SIOH component.
6.3.3
Non-Existent Hub Interface Devices
It is possible that the SIOH could have Hub Interface 2.0 ports that are not populated by any components. When RESETI# is deasserted, the SIOH samples REQ# on the Hub Interface 2.0 ports. If no component exists, then HLCTL[8] is not set. Once presence is detected, the HLCTL[2] default value is set appropriately. Any further transactions targeting a disabled interface are master aborted. Note: The default state of the Hub Interface enable bits (HLCTL[2]) is determined by whether a Hub Interface device is detected on the port or not. Software could choose to override this default setting by enabling or disabling that port.
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Reset
6.3.3.1
Non-Existent ICH4
For a large system implementing two SIOH components, only one of the SIOHs will interface a ICH4 component. Therefore, the SIOH without an ICH4 will attempt the reset handshake and the NOP will never complete. The default state of HLCTL[2] for function 0 is based on a successful or unsuccessful reset handshake. If the Hub Interface reset state machine completes normally, the interface is enabled. Otherwise, the interface remains disabled and any transactions targeting it are Master Aborted.
Note:
The default state of the Hub Interface enable bits (HLCTL[2]) is determined on whether a Hub Interface device was detected on the port or not. Software could choose to override this default setting by enabling or disabling that port.
6.4
Reset Signals
This section describes the different reset signals interfacing the SIOH.
6.4.1
PWRGOOD
PWRGOOD will be deasserted as the voltage supplies come up, or may be pulsed after power-on to clear the system. Slew rate requirements are specified in Section 8.8, "Miscellaneous Signal Group" . The assertion of power-good signal indicates that external clocks and power at the SIOH is stable.
6.4.2
RESETI#
This pin is the Hard Reset input to the SIOH. It may be driven by the ICH4 PCIRST# signal or, if determinism is required, by system reset control logic.
6.4.3
RESET66#
This pin is asserted in combination, while RESETI# is asserted asynchronously after PWRGOOD assertion or if the Hard Reset bit is set in the SIOH SYRE register. RESET66# will rise synchronous to CLK66. This pin will be driven to the P64H2 RSTIN# pin, requiring voltage level translation from 1.5V to 3.3V.
6.4.4
DET
The DET pin is strapped high to enable determinism in the SIOH. If high, CLK33 and CLK66 references are reset on first Hard Reset Deassertion. If this pin is low, the dividers that provide references for these clocks can come up at an arbitrary phase relative to the same clocks on other SIOHs and SNC memory maintenance operations.
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7.1 Data Integrity
7
Errors are classified into two basic types: fatal (or non-recoverable) and non-fatal (or recoverable).1 Fatal errors include protocol errors, parity errors on header fields, time-outs, failed link-level retry, etc. For fatal errors, continued operation of the chipset may be compromised. The SIOH can continue operations (transactions are completed, resources de-allocated, etc.) with non-fatal errors. Non-fatal errors are further classified into correctable and non-correctable errors. Non-correctable errors are those that are not "corrected" by the SIOH. Non-correctable errors may or may not be correctable by software. Correctable errors include single bit ECC errors, successful link level retry, and those transactions where the SIOH performs a master abort of the transaction. The SIOH indicates an error condition on external pins. A pin (open drain) is provided for each error type (fatal, uncorrectable, and correctable). It is up to the system to decide what is the best course of action upon the detection of an error. The SIOH provides error logging and error status for the first error detected by the component and error status for subsequent errors. Errors are detected and logged at intermediate entry points (on the inbound SP interface, for example). Errors are also detected and logged at the end points (where the packet is consumed or translated to another interface with different error coverage/detection). For data errors, the end-point is where the error is corrected or the data is poisoned2. This method of error correction and error logging is called end-to-end error correction. The data that is logged and the name of the error log is also listed. Some errors may be detected in more than one component, as is the case for many of the SP related errors.
7.1.1
End-to-End Error Correction
ECC errors are passed along to the end point. If the data path does not have ECC all the way, single-bit errors will be corrected just before the first ECC-less interface. Intermediate interfaces will not correct single-bit ECC errors. The ECC check bits and parity check bits are always passed along with data internally. A typical error will leave a trail behind in each component it passes. The system can use this to pinpoint source of error and recover from error conditions. The SIOH has the following end points for data: Hub Interface 1.5
* Outbound data cycles:
-- If no ECC error, generate good parity. -- If SBE, correct the error and generate good parity. -- If MBE, generate bad parity.
1. 2. These are hardware definitions used by the E8870 chipset, and are not the same error types that are used by software (MCA). ECC data is poisoned by flipping ECC check bits 7:1, which will result in a syndrome value of 11111110. Parity data is poisoned by flipping all of the parity bits associated with the data. Parity data is poisoned by flipping the parity bit.
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* Inbound data cycles:
-- If no parity error, generate good ECC. -- If parity error, generate poisoned ECC. PCI/PCI-X (performed by the P64H2)
* Outbound data cycles:
-- If no ECC error, generate good parity. -- If SBE, correct the error and generate good parity. -- If MBE, generate bad parity.
* Inbound data cycles:
-- If no parity error, generate good ECC. -- If parity error, generate poisoned ECC. Configuration Registers
* Writes:
-- If no ECC error, write the configuration register with data. -- If SBE, correct the error and write the configuration register with corrected data. -- If MBE, drop the write.
* Reads:
-- Generate good ECC from the data. Partial (unaligned to 8-byte boundary) Write Merge Buffers
* If no ECC error, merge the new data with the old and re-generate ECC. * If SBE on one or more 8-byte chunks, correct errors, merge the new data with the old and
re-generate ECC for the 8-byte chunks.
* If MBE on one or more 8-byte chunks, merge the new data with the old and poison the
8-byte chunks.
7.1.2
Error Reporting
The SIOH provides error status and logging registers that are specific to the E8870 chipset. The E8870 chipset specific registers are implemented in a similar manner across the chipset. In addition, the SIOH provides error status and log registers that are defined as part of the PCI standard interface. Below is a description of the E8870 chipset specific implementations. For details regarding the PCI specific registers, see the PCI Local Bus Specification, Revision 2.2.
7.1.2.1
Error Status and Log Registers
Error status registers are provided per component; FERRST (first error status register), and SERRST (second, or subsequent error status register). First fatal and/or first non-fatal errors are flagged in the FERRST register, subsequent errors are indicated in the SERRST. Associated with some of the errors flagged in the FERRST register are control and data logs. In some cases, the logs are duplicated for the same error (for example, two Hub Interfaces on the SIOH may have the same error log registers). When error logs are duplicated, a pointer to the cluster that reported the first error is provided.
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The contents of FERRST and SERRST are "sticky" across a reset (where power remains good). This provides the ability for firmware to perform diagnostics across reboots. Note that only the contents of FERRST effects the update of the any error log registers. To summarize, the rules for the FERRST and SERRST registers and error logs are as follows: 1. First fatal and first non-fatal (uncorrectable, correctable) errors are flagged in the FERRST. For example, if a correctable error has been flagged, and a fatal error is detected, the FERRST should be updated to indicated that a fatal error has been detected as well. Both errors will be flagged in the FERRST. At most two bits will be asserted in the FERRST. 2. If more than one fatal error is detected simultaneously, the error with the MSB in the FERRST will be selected. If more than one non-fatal error is detected, uncorrectable errors will be selected to be flagged before correctable errors. If two errors of the same sub-type are detected, the MSB algorithm is applied. 3. If more than one fatal error is detected simultaneously, one is selected to be flagged in the FERRST, the other is flagged in the SERRST. The same algorithm applies to non-fatal errors. 4. In the case where there are multiple duplicate log registers for an error, a pointer to the unit reporting the error is updated in FERRST. 5. FERRST, SERRST and error log registers are sticky across reset (where PWRGOOD remains asserted).
7.1.2.2
Error Signaling
Three open-drain error pins are associated with each of FERRST/SERRST registers, one for each error type: fatal, uncorrectable and correctable (ERR[2:0]# respectively). If not masked (ERRMSK register), these pins will reflect the error status of each type in the two error status registers. The value of the error pins when an error is flagged is also stored in the FERRST to facilitate the identification of the first error in the system. For example, when a first fatal error detected on the component, the value of the error status pin associated with fatal errors is also latched into the FERRST. For reliable signaling of errors in the system, each component guarantees that the pin associated with the error is asserted within four system clock cycles (200 MHz) after the error is detected by the component. For example, if a multi-bit ECC error is detected at the SP interface in cycle x, the uncorrectable error pin (ERR[1]#) is asserted in cycle x+3. The error pins are asynchronous I/O signals.
7.1.2.3
Error Logs
Control and/or data logs are provided for some errors. The "non-recoverable" error logs are used to log information associated with first fatal errors. The "recoverable" error logs are used for first non-fatal errors. Once a first error for a type of error has been flagged (and logged), the log registers for that error type remain fixed until either 1) all bits associated with the error type in the FERRST are cleared, or 2) a power-on reset. More specifically, when the status bits associated with fatal errors are cleared in FERRST, updates to the non-recoverable error logs are enabled. When the status bits associated with non-fatal errors are cleared in FERRST, updates to the recoverable error logs are enabled.
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7.1.3
Interface Details
Major interfaces in the chipset can be enabled/disable via software to aid fault isolation. Any requests routed to a disabled interface will be master-aborted. Any responses will be absorbed. That is, no issue is required on the disabled interface, but the disabled interface must not assert internal flow control. Scalability Port
* Data is protected by ECC. ECC is checked only on entry of packets. * Flits transfers are protected by parity. * The information contained in the SP control and idle flits packet are protected by both parity
and duplication (each field is duplicated on different wires to enhance error detection).
* Link level retry is supported on the SP. Link level retry is entered when parity errors are
detected on flits, or when phits within an idle flit have a duplication error.
* Whenever the SIOH returns a Master Abort status, a PCMP_D completion is returned where
the data length is zero. In the case where the SIOH receives a failed response status, the error is reported immediately to FERRST/SERRST but the transaction continues as if the completion was normal. When a failed response status is received, the transaction may not be able to complete. (For instance, a PRIL may receive the data, but never the PCMP due to the failure). Hub Interface 2.0 Interfaces
* Protected by ECC:
-- ECC checking disabled with HLCTL.
* Inbound transactions that receive a failed response are discarded. A Target Abort will be
returned to the initiator with enough data phases to match the initial request.
* Special cycle errors are logged by the SIOH.
Hub Interface 1.5 Interfaces
* 1 parity bit per 32-bit data:
-- Parity checking disabled with HLCTL.
* Special cycles will be logged by SIOH. * Inbound transactions with fatal errors are discarded. A hard fail completion packet will be
returned to the initiator.
* Outbound transactions that encounter fatal errors like target abort should be terminated with
hard fail completion (needs support from ICH4). PCI-X/PCI
* Parity bits are generated and checked independently for each PCI bus:
-- Parity checking disabled with PCICMD.
* Standard PCI checking for aborts, PERR# and SERR# are also done. * Parity errors or aborts can be configured to assert SERR# special cycles on Hub Interface. The
SIOH will log the SERR cycles and assert its error pins.
* Upon receiving hard fail completion from Hub Interface, the failed transaction on PCI-X/PCI
will be terminated with target abort (needs support from P64H2 and ICH4).
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Configuration Register
* ECC is checked on configuration writes.
Partial Write Merge Buffer
* ECC is checked before the merge.
SMBus
* The SMBus port supports the optional Packet Error Correction feature of SMBus
Specification, Revision 2.0. This feature allows the slave to append an 8-bit CRC to read completions.
7.1.4
Time-Out
When an entry in the LRB is allocated, it becomes valid and is tracked by the master timer logic. The timer is a 24-bit wrap-around counter, incrementing at 25 MHz (200 MHz core clock divided by 8).The time-out period is programmable (a value in the ERRCOM register that determines the size of the counter). The timer interval must be greater than the worst case latency required in the system to de-allocate the queue entry. For example, the LRB interval must be set to greater than the worst case latency from the SP issue to the response, including contention scenarios for all resources the request must acquire. An entry times-out if the counter wraps around (toggles the high-order) bit twice. As a result, the time-out period can be from 1x to 2x the timer value. It is possible for multiple entries in a queue to time-out simultaneously. When a time-out occurs, the hardware selects one entry as the "first error" for logging. The presence of more than one error is indicated in the SERRST registers.
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Electrical Specifications
8.1 Non-Operational Maximum Rating
8
The absolute maximum non-operational DC ratings are provided in Table 8-1. Functional operation at the absolute maximum and minimum ratings is neither implied nor guaranteed. The SIOH should not receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and operational DC tables. Furthermore, although the SIOH contains protective circuitry to resist damage from static discharge, one should always take precautions to avoid high static voltages or electric fields. Table 8-1. Absolute Maximum Non-Operational DC Ratings at the Package Pin
Symbol Tstorage Vcc (All) Parameter SIOH Storage Temperature SIOH Supply Voltages with Respect to Vss CMOS Buffer DC Input Voltage with Respect to Vss Min -10 -0.50 Max 45 Operating voltage + 0.50 Vcc (CMOS) + 0.50 Unit C V Notes
Vcc (CMOS)
-0.50
V
8.2
Operational Power Delivery Specification
The SIOH power requirements are outlined in this section. All parameters in Table 8-2 are specified at the pin of the component package.
Table 8-2. Voltage and Current Specifications
Symbol Vcc15 ICCCore dICC/dtCore Vccsp Isp dIsp/dt Vcc18= Vth1 Vcc18-ICC= Ith1 dIvcc18=dIth1/dt Vcc33 Vcc33-ICC Parameter Core Voltage Core Current Core Transient Slew Rate Scalability Port Supply Voltage Scalability Port Current SP Transient Slew Rate 1.8 Supply Voltage 1.8 Supply Voltage Transient Current 1.8 Supply Voltage Transient Slew Rate 3.3 Volt Supply 3.3 Volt Transient Supply Current 3.135 3.3 1.71 1.8 1.209 1.30 Min 1.425 Typical 1.5 Max 1.575 12.6 2.0 1.391 0.50 1.0 1.89 0.70 1.00 3.465 0.10 Unit V A A/ns V A A/ns V A A/ns V A
h b, c, d a
Notes
e, f g
a. The maximum ICC current is the worst case specification, (i.e. Vcc max, low temperature and application mix) intended for power supply design. b. Vccsp budget is 3% DC, and (DC + AC) at 7% noise delivered at the pin.
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Electrical Specifications
c. The power pins are separated at the package from the Vcc core or other supplies on-die. d. The power supply must be local to each component. The SP power supply between two communicating ports needs to be separate. e. The current requirement per scalability port (SP) port. f. Under normal operating conditions. However, under certain test conditions, Isp might exceed the specification. g. The specification is per SP port at the package pin. h. I2C circuitry does not contribute significantly to the 3.3V transient load.
8.3
Scalability Port (SP) Signal Group
The SP interface is a source-synchronous interface with coincident data and continuous strobe transmission. The data and strobe signals are launched simultaneously and are expected to arrive at the receiver with the same timing relationship to one another. Each SP port consists of two strands that are further subdivided into two bundles. Each SP port consists of thirty-two data bits, four 4 ECC bits, two parity bits, two SSO coding bits, two link layer control (LLC) bits, four strobe pairs (eight signal pins), reserved pins, and eight reference voltage pairs (sixteen signal pins). The simultaneous bi-directional (SBD) signaling can create conditions for three logic levels on the interconnect (0, 0.65, 1.3)V, depending on the data values driven from each end of the trace. All SBD signals are terminated via on-die termination. The reference voltages are generated on die and are set to 1/4Vccsp and 3/4Vccsp, so no external logic is needed to generate these reference voltages. Each SP voltage reference pin is required to be interlinked to the corresponding SP port. Table 8-3 summarizes the signal grouping of the SP interface. The "x" in the signal names is replaced with the specific SP port on the SIOH (0 or 1).
Table 8-3. Scalability Port Interface Signal Group
Signal SBD I/O Signal Description SPxAD[15;0],SPxBD[15;0], SPxASTBP[1:0], SPxASTBPN[1:0], SPxBSTBP[1:0], SPxBSTBPN[1:0], SPxAEP[2:0], SPxBEP[2:0], SPxALLC, SPxBLLC, SPxASSO, SPxBSSO SPxGPIO[1:0] SPxPRESa SPxSYNCa Vccspb, Vss SPxZUPD[1:0]d, SPxAVREFH[3:0], SPxBVREFH[3:0], SPxAVREFL[3:0], SPxBVREFL[3:0]e VCCASPe, VSSASP
CMOS1.5 I/O ODa CMOS1.3 INPUTa CMOS1.3 I/O Power/Other Analog I/Oc SP Analog Input
a. b. c. d.
See Section 8.8 for "CMOS1.3" specifications. Vccsp is to be supplied to the SP port externally. See Table 8-2. Reference voltages are generated on-die. SPxZUPD0 impedance update pins are connected through a 45-ohm, 1% resistor to Vccsp; SPxZUPD1 impedance update pins are connected through 45-ohm, 1% resistor to Vss. e. PLL analog voltage for SP, connected on the motherboard to Vcc15 supply (1.5V nominal 5%) through a filter network. See Section 8.8.
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Electrical Specifications
8.4
Hub Interface 2.0 (HI 2.0) Signal Group
The HI 2.0 is a 16-bit source-synchronous interface. All signals are terminated on-die at the receiver end of the interface to Vss. Table 8-4 summarizes the HI 2.0 signal groups. Unless otherwise noted, all specifications are at the component die pad. Note: The P64H2 and ICH4 Hub Interface specifications are published independently.
Table 8-4. Hub Interface 2.0 Signal Groups a, b
Signal Group Source-Synchronous I/O Common Clock, Output Common Clock, Input Common Clock, IO Analog Input
a. b. c. d.
Type iGTL+ iGTL+ iGTL+ iGTL+ iGTL+
Signal Description HLxPD[17:0], HLxPSTRB[F,S], HLxPUSTRB[F,S] HLxRQout HLxRQin HLxSTOP, HLxIOH HLxVswingc, HLxVrefc, HLRcomp d, VCCAHLe, VSSAHL
iGTL+ means "inverted" GTL+. The signal name x is replaced with the hub port number on the device (1-4) for SIOH. Vref and Vswing are supplied on the motherboard. Rcomp value is equal to [Zo * (Vcc-Vswing) /Vswing]. Zo = nominal HI 2.0 trace impedance; Vswing = 0.8V; Vcc = typical HI voltage = 1.5v for SIOH HI 2.0. e. Connected to 1.5V 5% on the motherboard.
8.4.1
Hub Interface 2.0 DC Specifications
a, b, c Min 1.425 -0.3 Vref + 0.1 0.05 Vswing - 0.05 Vswing +0.05 100 100 -19.6 5 5 8 0.5 Max 1.575 Vref - 0.1 Unit V V V V V A A mA pF pF pF
g d d e, f e, f
Table 8-5. Hub Interface 2.0 DC Parameters
Symbol Vcc Vil Vih Vol Voh Ili Ilo Ioh Cin Cclk Cin
a. b. c. d. e. f. g.
Parameter Driver Power Rail Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Leakage Current Output Leakage Current Output High Current Input Capacitance Clock input Capacitance Strobe to Data Capacitance Difference
Notes
All specification are at the die pad. Parameters apply to all inputs, outputs and I/O buffers. All voltages are referenced to Vss. Vilmin is a function of the process. Vihmax is not defined explicitly but is a function of Voh across the transmission line. Vol@ 1mA. Voh@ (0.6/Zo) mA. Volmin and Vohmax are not valid DC operating points. Measured as (Vswing +10%)/(Zo-10%).
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Table 8-6. Hub Interface 2.0 Reference Voltages a, b, c, d, e
Symbol HLxVref HLxVswing Parameter HI 2.0 Reference Voltage HI 2.0 Reference Swing Voltage Min 0.343 0.784 Typical 0.35 0.80 Max 0.357 0.816 Units V V Notes
f f, g, h
a. All specifications are at the die pad. b. Resistor-divider chain implemented to generate reference and swing voltages should use less than 1k-ohm resistors in order to ensure the reference voltage tolerance is met over the input leakage specification. c. All voltages are referenced to Vss and generated from VCC15. d. Uncorrected noise must be controlled to less than 10% peak to peak of the swing. This tight tolerance is required in order to have enough noise margin for the incoming signal. e. Based on a 1% divergent variation of resistive ladder. Numbers will additionally scale with Vcc variation. f. Hub Interface 2.0 reference and swing voltage generation circuitry must be capable of supplying 500 A while maintaining DC specifications. g. Change to the Hub Interface specification requires reference swing voltage to be 0.8V. h. This pin feeds a high impedance input requiring about 50mA of current.
8.5
Hub Interface 1.5 (HI 1.5) Signal Group
The 8-bit Hub Interface is designated as HL0 of the five Hub Interfaces supported on the SIOH.
8.5.1
.
HI 1.5 Signal Groups
The HI 1.5 is an 8-bit source-synchronous interface for data transfer. All signals are terminated ondie to Vss at the receiving end of the interface. Table 8-7 summarizes the signal groups for HI 1.5.
Table 8-7. Hub Interface 1.5 Signal Group a, b
Signal Group Source Synchronous, I/O Common Clock, I/O Common Clock, Output Common Clock, Input Analog Input
a. b. c. d. e. f.
Type iGTL iGTL iGTL iGTL NA HLPD[7:0]#, HLSTRB[S,F]# HLSTOP#,HLPAR# HL0RQOUT# d HL0RQIN#d
c
Signal
HL0RCOMP e, HL0VSwingf, HL0VREFf
HI 1.5 signals are all active high asserted on the bus. iGTL means "inverted" GTL with receiver terminated through on die NMOS-resistors to Vss. Strobes are defined as HLSTRBF (first) and HLSTRBS (second). The HL0RQIN# signal of the SIOH will connect to the RQOUT# signal of the opposing chip and vice versa. Please see Section 8.6.1. for RCOMP details. Reference and swing voltages are supplied from the motherboard.
8.5.2
Hub Interface 1.5 DC Specifications
a, b, c, d Min 1.71 Vref+0.1 -0.3 0.65 Max 1.89 1.2 Vref-0.1 0.75 Units V V V V
e
Table 8-8. Hub Interface 1.5 DC Signaling Specifications
Symbol Vcc Vih Vil Voh Parameter Driver Power Rail Input High Voltage Input Low Voltage Output High Voltage
Notes
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Table 8-8. Hub Interface 1.5 DC Signaling Specifications (Continued) a, b, c, d
Symbol Vol Ioh Cin Cclk Cin
a. b. c. d. e. f. g.
Parameter Output Low Voltage Output High Current Input Capacitance Clock input Capacitance Strobe to Data Capacitance difference
Min
Max 0.05
Units V mA
Notes
f g
16 5 5 8 0.5
pF pF pF
All specifications are at the pin of the package. All voltages are referenced to Vss. Parameters apply to all inputs, outputs and I/O buffers. All input and output signal levels must comply with the Vil min, ViH max specification. Iout = 0.8/ZTarget. Iout = 1mA. Measured at Voh = Vswing/50.
Table 8-9. SIOH Hub Interface 1.5 Reference Voltages a, b, c, d, e
Symbol HL0Vref HL0Vswing Parameter HI 1.5 Reference Voltage HI 1.5 Reference Swing Voltage Min 0.343 0.784 Typical 0.35 0.8 Max 0.357 0.816 Unit V V Notes
f f, g, h
a. All specifications are at the pin of the package. b. Resistor-divider chain implemented to generate reference and swing voltages should use less than 1k-ohm resistors in order to ensure the reference voltage tolerance is met over the input leakage specification. c. Vcc18 is the driver power supply from which both references are generated. d. Uncorrected noise must be controlled to less than 10% peak to peak of the swing. This tight tolerance is required in order to have enough noise margin for the incoming signal. e. This range accounts for 1% divergent variation of the reference voltage generation resistors. The reference voltage will, in addition, vary linearly with Vcc18. f. The reference and swing voltage generation circuitry must be capable of supplying 500 uA while maintaining DC specifications. g. Change to the Hub Interface specification reconnects HI 1.5 reference swing voltage to be 0.8V. h. This pin feeds a high impedance input requiring about 50mA of current.
8.6
8.6.1
Analog Inputs
Hub Interface Impedance Compenstation (RCOMP)
The RCOMP pin is to be connected through a resistor to the appropriate voltage rail to make impedance compensation possible. The value of the resistor changes depending on the characteristic impedance of the bus. See Table 8-10 for details. Note: In all cases, use [1%-tolerance, 1/4 watt] or better resistors.
Table 8-10. Table of Values for the RCOMP Resistor
Component Interface HI 2.0a HI 1.5
b
50-ohm Bus 43.2 50
60-ohm Bus 52.3 60
Tied To: Vcc15 GND
a. HI 2.0 RCOMP = [Z0 * (VCC15 - Vswing) / Vswing]. ZO = nominal HI trace impedance; Vcc = typical HI voltage = 1.5v for SIOH HI 2.0. b. HI 1.5 RCOMP = ZO to GND. This is SIOH-dependent for HI 1.5 support. This requirement does not apply to the ICH4 component.
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Electrical Specifications
8.6.2
Hub Interface Vref/Vswing Decoupling
Decoupling capacitors used for HI2.0 and HI1.5 Vref/Vswing decoupling must have low equivalent series resistance (ESR) and inductance (ESL). The Vref/Vswing generator and its decoupling must be placed close to the HI interface to derive the benefit of accurately capturing the effect of power supply variations. Generic guidelines would be a 0.1 uF decoupling capacitor placed as close as possible to the Vref/ Vswing generation resistor divider circuit, and a 0.001 uF bypass capacitor placed as close as possible to the Vref/Vswing pin. If the Vref/Vswing divider is shared by multiple chips over a distance of greater than 1 inch, then each interface should have its own 0.001 uF bypass cap placed as close as possible to the Vref/ Vswing pins. Noise coupling from other signals should be kept to less than 20 mV. The trace spacing around the Vref/Vswing signal should be a minimum of .025 inches (25 mils) or 5X the dielectric thickness (whichever is greater) to reduce the crosstalk and maintain signal integrity.
8.7
SMBus and TAP Signal Group
The SIOH shares the same SMBus and TAP signal groups as the SNC and SPS components of the E8870 chipset, and uses open-drain outputs and its own defined logic levels, which are different than CMOS logic levels. The TAP connection input signals require external termination. No reference voltage is required for these signals. The SMBus and TAP signals require termination to 3.3V and 1.5V on the motherboard, respectively. For specifications for related components, or external tools that will interface with the SIOH, refer to that component's or tool's associated specification.
Table 8-11. SMBus and TAP Interface Signal Group a
Signal Group SMBus (I/O) TAP (Input) TAP (Output) Signal Description SPDCLK, SPDDA, SCL, SDA TCK, TDI, TMS, TRST# TDO
a. I/O designations are with respect to the SIOH component.
Table 8-12. TAP Signal Terminations a, b
TCK TMS TDIc TDO, TDI TRST# 27-ohm to GND 39-ohm to Vcc 150-ohm to Vcc 75-ohm to Vcc 500- to 680-ohm to GND
a. Termination values for input pins are based on requirements of Intel's in-target probe. Requirements for other applications may differ. b. All resistances are nominal with a tolerance allowance of 5%. c. This TDI pull-up value applies only to TDI inputs driven by Intel's in-target probe TAP controller.
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8.7.1
SMBus and TAP DC Specifications
Table 8-13. TAP DC Parameters a
Symbol Vil Vih VTV T+ VH Vol Ili Iol Parameter Input Low Voltage Input High Voltage Negative-going Threshold Voltage Positive-going Threshold Voltage Hysteresis Voltage Output Low Voltage Input Leakage Current Output Low Current 12.7 Min -0.4 1.16 0.76 0.91 130 0.34 0.49 50 Max 0.76 1.8 1.03 1.16 Unit V V V V mV V A mA
b b b c c c
Notes
a. All specifications are at the pin of the package. b. See Figure 8-1. c. Measured with a 75-ohm 10% test load to Vcc.
Figure 8-1. TAP DC Thresholds
V T + (max) V T + (min) VT - (min)
001258
TAP Signal
V H (min) VT V H (min)
(max)
Table 8-14. SMBus DC Parameters a, b
Symbol Vil Vih Vol Ili Ipullup Cin Vnoise
a. b. c. d. e.
Parameter Input Low Voltage Input High Voltage Output Low Voltage Input Leakage Current Current through Pull-up Resistor Input Capacitance Signal Noise Immunity
Min -0.5 2.1
Max 0.8 3.47 0.4 50
Unit V V V A mA
Notes
c
4.0 10 300
pF mV
d, e
All specifications are at the pin of the package. Parameters apply to SMBus inputs, outputs and I/O buffers. At Vol max, Iol = 4 mA. At 1 MHz to 5 MHz range. Peak-to-peak.
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8.7.2
SMBus and TAP AC Specifications
Table 8-15. SMBus Signal Group AC Specifications a
Symbol fsmb T60 T61 T62 Tr Tf Parameter Operating Frequency SMBus Output Valid Delay SMBus Input Setup Time SMBus Input Hold Time Clock/Data Rise Time Clock/Data Fall Time Bus Free Time 4.70 250 300 1000 300 Min 10 Max 100 1.0 Unit kHz us ns ns ns ns us
b c d
Notes
a. All AC timings for the SMBus signals are referenced to the SM_CLK signal at 0.5 * SM_VCC at the package pins. All SMBus signal timings (SM_DAT, SM_ALERT#, etc.) are referenced at 0.5 * SM_VCC at the package pins. b. Tr = (Vil,max-0.15) to (Vih,min+0.15). c. Tf = (Vih,min+0.15) to (Vil,max-0.15). d. Minimum time allowed between request cycles.
Table 8-16. TAP Signal Group AC Specifications a
Symbol TCK Frequency T58 T59 TCK, TMS, TDI Rise Time TCK, TMS, TDI Fall Time TDO Rise Time TDO Fall Time T60 T61 T62 TRST#
a. b. c. d.
Parameter
Min 1.0 0.5 0.5 2.3 1.2 2.5 5 18 300
Max 20 16 16 4.6 5.3 10
Unit MHz ns ns ns ns ns ns ns ns
Notes
b c c c c d, e e
TDO Clock to Output Delay TDI, TMS Setup Time TDI, TMS Hold Time Assert Time
All AC timings for the TAP signals are referenced to TCK at 50% voltage level. Rise and fall times are measured from the 20% to 80% points of the signal swing. Referenced to the falling edge of TCK. Specification for a minimum swing defined between TAP V IL_MAX to V IH_MIN. This assumes a minimum edge rate of 0.5V per ns. e. Referenced to the rising edge of TCK at the component pin.
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8.7.3
SMBus and TAP AC Timing Waveforms
Figure 8-2. TAP and SMBus Valid Delay Timing Waveform
Clock
Tx
Ts
Th
Signal
V
Valid
Tx Ta Th V
= = = =
T60 (Valid Time) T61 (Setup Time) T62 (Hold Time) 0.5* SM_Vcc for SMBus Signal Group
Figure 8-3. TCK and SM_CLK Clock Waveform
Tr Th
*V2 Clock *V1
Tf Tp
Tr Tf Th Tl Tp = = = = = T58, T74 (Rise Time) T59, T75 (Fall Time) T72 (High Time) T73 (Low Time) T55 (TCK, SM_CLK Period)
Tl
V1, V2: For rise and fall times, TCK and SM_CLK are measured between 20% and 80% points.
8.8
Miscellaneous Signal Group
All buffer types that do not belong to one of the major buses in the system are listed as miscellaneous signals (refer to Table 8-17).
Table 8-17. Miscellaneous Signal Group
Signal Group CMOS1.3 Input CMOS1.3 I/O CMOS1.5 I/O OD CMOS1.5 O OD SPxPRES SPxSYNC ERR[2:0]#, EV[3:0]#, SPxGPIO[1:0] INT_OUT# Signal Description
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Table 8-17. Miscellaneous Signal Group (Continued)
Signal Group CMOS1.5 Input CMOS1.5 Output ANALOG INPUT VCC Signal Description BUSID[2:0], LVHSTLODTEN, NODEID[4:0], PWRGOOD, RESETI#a, DET RESET66# VREFFBCLK66, VCCACOREb, VSSACORE
a. Requires external 330-ohm pull-up resistor. b. PLL analog voltage input for core PLL, connect to 1.5V 5% through a network filter.
Table 8-18. VREFFBCLK66 Reference Voltage a, b
Symbol Vreffbclk66 Parameter SIOH 66 MHz Feedback Clock VREF Min 1.568 Typical 1.65 Max 1.733 Unit V Notes
a. All specifications are at the pin of the package. b. Vreffbclk66 = Vcc33/2.
8.8.1
Miscellaneous Signal DC Specifications
Table 8-19. CMOS 1.3V DC Parameters a, b
Symbol Vil Vih Vol Voh Ili Ron_p Ron_n Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Leakage Current On-Resistance P-device On-Resistance N-device 300 27 Min -0.3 1.11 -0.15 1.21 Max 0.35 Vccsp + 0.3 0.26 1.39 10 700 72 Unit V V V V A ohms ohms
c c
Notes
a. All specifications are at the pin of the package. b. Parameters apply to all CMOS 1.3V buffer types unless otherwise noted. c. Parameters are not applicable to the "CMOS 1.3V Input" signal group.
Table 8-20. CMOS 1.5V Open Drain DC Parameters a
Symbol VIH VIL VoH VoL Iol Ili Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Current Input Leakage Current Min 1.15 -0.3 1.3 Max Vcc + 0.3 0.70 Vcc + 0.3 0.54 52.0 50 Unit V V V V mA A
b c c
Notes
a. Supply voltage at 1.5V 5% tolerance. b. RI = 50 or 25 Ohms. c. RI = 25 Ohms.
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Table 8-21. CMOS 1.5V DC Parameters a
Symbol VIH VIL VoH VoL Vhysteresis Ron Ili Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Hysteresis Voltage Output Impedance Input Leakage Current 0.10 30 80 70 Min 0.90 -0.30 0.8*Vcc Max Vcc+0.3 0.50 Vcc+0.3 0.20*Vcc Unit V V V V V ohms A Notes
a. Supply voltage at 1.5V 5% tolerance.
8.8.2
Miscellaneous Signal AC Specifications
Table 8-22. CMOS 1.3V Open Drain AC Parameters a
Symbol Tco Tsu Thold SRf SRr Parameter Clock to Output Valid Delay Input Setup Time Input Hold Time Output Slew Rate Fall Output Slew Rate Rise Min 0.15 N/A N/A 0.25 0.5 0.7 15.0 Max 15.0 Unit ns ns ns V/ns V/ns Notes
a. Clock delay is in reference to the 200 MHz clock.
Table 8-23. CMOS 1.5V Open Drain AC Parameters a, b, c
Symbol Tco Tsu Thold SRf SRr Parameter Clock to Output Valid Delay Input Setup Time Input Hold Time Output Slew Rate Fall Output Slew Rate Rise Min 0.15 0.98 0.38 0.25 0.37 0.91 1.18 Max 2.69 Unit ns ns ns V/ns V/ns
e e
Notes
d, e
Signal: INT_OUT# Tco
a. b. c. d. e.
Clock to Output Valid Delay
8.3
ns
Supply voltage at 1.5V 5% tolerance. Clock delay is in reference to the 200 MHz clock. Specification doesn't apply to signals EV[3:0]#, ERR[2:0]#, SPxGPIO[1:0]. See Table 8-25. Specification doesn't apply to INT_OUT#. RI = 25 ohms.
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Table 8-24. CMOS 1.5V Input AC Parameters a, b
Symbol Tco Tsu Thold SRf SRr Parameter Clock to Output Valid Delay Input Setup Time Input Hold Time Output Slew Rate Fall Output Slew Rate Rise Min -0.28 0.84 0.35 2.00 1.90 5.00 4.9 Max 1.44 Unit ns ns ns V/ns V/ns Notes
c
Signal: RESET66# Tco Clock to Output Valid Delay 1.7 ns
a. Supply voltage at 1.5v 5% tolerance. b. Clock delay is in reference to the 200 MHz clock. c. Specification doesn't apply to RESET66#.
Table 8-25. CMOS 1.5 I/O Open Drain AC Parameters
Symbol Signals: EV[3:0]#, ERR[2:0]# Tco Tsu Thold SRf SRr Clock to Output Valid Delay Input Setup Time Input Hold Time Output Slew Rate Fall Output Slew Rate Rise 1.9 0.9 0.20 0.25 0.37 0.91 1.18 5.2 ns ns ns V/ns V/ns Parameter Min Max Unit Notes
Signal: SPxGPIO[1:0] Tco Tsu Thold SRf SRr Clock to Output Valid Delay Input Setup Time Input Hold Time Output Slew Rate Fall Output Slew Rate Rise 2.5 -2.0 0.25 0.37 0.91 1.18 6.7 ns ns ns V/ns V/ns
8.9
Clock Signal Groups
Table 8-26. Clock Signal Groups
Signal Group LVHSTL Differential Inputs Signals SYSCLK, SYSCLK#
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Table 8-27. LVHSTL Clock DC Parameters
Symbol VIH VIL VX CCLK Parameter Input High Voltage Input Low Voltage Input Crossover Voltage Input Capacitance Min 0.78 -0.3 0.55 1.0 Typ Max 1.3 0.5 0.85 11.5 Unit V V V pF
8.9.1
AC Specification
Table 8-28. LVHSTL Differential Clock AC Specification
Symbol Tperiod fBCLK Tjitter Thigh Tlow Trise Tfall VPP Parameter SYSCLK Period SYSCLK Frequency SYSCLK Input Jitter SYSCLK High Time SYSCLK Low Time SYSCLK Rise Time SYSCLK Fall Time Minimum Input Swing 2.25 2.25 333 333 2.5 2.5 500 500 600 200 Min Typ 5.0 200 100 2.75 2.75 667 667 Max Unit ns MHz ps ns ns ps ps mV Notes
a a, b a, c a, d a a a a, e
a. See Figure 8-4. b. Measured on cross point of rising edge of SYSCLK and falling edge of SYSCLK#. Long term jitter is defined as peak-to-peak variation measured by accumulating a large number of clock cycles and recording peak-to-peak jitter. c. Long term jitter is defined as peak-to-peak variation measured by accumulating a large number of clock cycles and recording peak-to-peak jitter. d. Measured on cross point of rising edge of SYSCLK and falling edge of SYSCLK#. e. VPPmin is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing.
Figure 8-4. Generic Differential Clock Waveform
Thigh Trise Vpp 80% 20% Tperiod BCLKP Tlow Tfall BCLKN Tjitter
Trise = Rise Time Tfall = Fall Time Thigh = High Time Tlow = Low Time
Tperiod = Period Tjitter Vpp = Long Term Peak-to-Peak Jitter = Peak-to-Peak Swing
000615
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8-14
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9.1 1012-Ball OLGA2b Package Information
9
The 1012-ball OLGA2b package of the SIOH has an exposed die mounted on a package substrate. The package's coplanarity has a mean of approximately 8-mils and a tolerance at 4-sigma of approximately 4-mils. A heatsink, with appropriate interface material and retention capabilities, is required for proper operation (refer to Figure 9-1 and Figure 9-2). Figure 9-1. 1012-Ball OLGA2b Package Dimensions - Top View
Handling Exclusion Area Die Keepout Area
0.829 in. 0.529 in. 0.100 in. 0.200 in.
0.100 in.
0.870 in. 0.670 in.
SIOH Die
28.50 mm 32.50 mm 42.50 mm
0.100 in. 28.50 mm 32.50 mm 42.50 mm
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Package and Ballout
Figure 9-2. 1012-Ball OLGA2b Package Dimensions - Bottom View
0.635
21.250
1.270
AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1.270 19.685
-A-
2 x 1.465 Min. -B-
39.370 2 x 42.500 0.100 0.200 A B
NOTE: All dimensions are in millimeters.
001250
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Figure 9-3. 1012-Ball OLGA2b Solder Ball Detail
H OLGA Substrate Die Solder Bumps 0.74 0.025 0.100 0.025
Underfill Epoxy 1.300 0.100 0.600 0.100 Die J Detail J
2.140 0.150
BGA Solder Balls
Detail H
NOTE: All dimensions are in millimeters.
001248
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9.2
Ballout - Signal List
Ball Number A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 B2 B3 B4 B5 B6 B7 B8 B9 B10 Vss Vcc Vss HL4PD[15] Vss HL4PUSTRBS Vss HL4PD[9] Vcc HL4PD[6] Vss HL4PD[4] Vss HL4PD[0] Vcc18 HL0PD[6]# Vss HL0PSTRBS Vss HL0PD[0]# Vss SP1BD[13] Vss SP1BD[15] Vss SP1BD[12] Vss SP1BSSO Vss Vcc Vss Vcc Vcc HL4PD[13] Vss HL4PD[11] Vss Signal Ball Number B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 HL4PD[16] Vss HL4PSTRBF Vss HL4PD[2] Vss HL0VREF[0] Vss HL0PSTRBF Vss HL0PD[2]# Vss SP1BD[14] Vccsp SP1BVREFL[3] Vss SP1BVREFH[3] Vccsp SP1BD[11] Vss SP1BD[5] Vss Vcc Vss Vcc Vss HL4PD[17] Vss HL4PUSTRBF Vss HL4PD[10] Vcc HL4PD[7] Vss HL4PSTRBS Vss HL4PD[1] Signal
Table 9-1. SIOH Ball List
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Table 9-1. SIOH Ball List (Continued)
Ball Number C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 Signal >= 1k-ohm P/D HL0PD[7]# Vss HL0PD[4]# Vcc18 HL0PD[1]# Vss SP1BD[10] Vss SP1BRSVD Vss SP1BD[6] Vss SP1BD[7] Vss SP1BD[4] Vcc Vss Vcc Vss Vcc Vss HL4PD[14] Vss HL4PD[12] Vss HL4PD[8] Vss HL4PD[5] Vss HL4PD[3] Vcc Vss Vcc18 HL0PD[5]# Vss HL0PD[3]# Vss 330-ohm P/D Ball Number D24 D25 D26 D27 D28 D29 D30 D31 D32 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 Vss SP1BSTBN[1] Vccsp SP1BSTBP[1] Vss SP1BVREFL[1] Vccsp SP1BVREFH[1] Vss HL3PD[0] Vss HL3PD[1] Vcc HL3RCOMP HL4RQOUT Vcc HL4STOP Vss HL4RQIN Vss HL4VREF[1] Vcc HL4VSWING Vss HL4RCOMP HL0RCOMP HL0STOP# Vss HL0PAR# Vss N/C Vss SP1BD[9] Vss SP1BLLC Vss SP1BEP[0] Vss SP1BD[3] Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number E31 E32 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 G1 G2 G3 G4 G5 Vss SP1BD[2] Vss HL3PD[2] Vss HL3PD[3] Vss N/C Vss N/C HL4VREF[0] LVHSTLODTEN CLK66 Vss CLK33 330-ohm P/D 330-ohm P/D Vss HL0VSWING HL0RQIN# HL0RQOUT# Vcc18 HL0VREF[1] Vcc18 SP1PRES Vccsp SP1BVREFH[2] Vss SP1BVREFL[2] Vccsp SP1BSTBN[0] Vss SP1BSTBP[0] Vss HL3PD[4] Vss HL3PSTRBS Vss HL3VSWING Signal Ball Number G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 Vss N/C Vss 330-ohm P/D N/C Vcc N/C DET 330-ohm P/D Vcc N/C 330-ohm P/D N/C Vss VCCACORE VSSACORE VssAHL SP1SYNC N/C Vss SP1BD[8] Vss SP1BEP[2] Vss SP1BD[1] Vss SP1BEP[1] Vss HL3PSTRBF Vss HL3PD[5] Vcc HL4VREF[2] Vcc 330-ohm P/D 330-ohm P/D Vss N/C N/C Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 Signal 330-ohm P/D Vss 330-ohm P/D 330-ohm P/D N/C Vss SYSCLK# VCCASP VssASP Vss SP1ZUPD[0] Vss SP1AD[8] Vccsp N/C Vss SP1BVREFH[0] Vccsp SP1BVREFL[0] Vss HL3PD[6] Vss HL3PD[7] Vss HL3VREF[1] Vss Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 330-ohm P/D VCCAHL Ball Number J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 SYSCLK Vss FBCLK66 Vss SP1AVREFL[2] Vss SP1AVREFH[2] Vss N/C Vss SP1BD[0] Vss SP1AD[0] Vcc HL3PD[16] Vcc HL3PD[8] Vss HL3VREF[0] Vcc Vss Vcc Vcc Vcc Vss Vcc Vcc Vcc Vss Vcc Vcc VCCACOM VCC33 VssACOM VREFFBCLK66 SP1ZUPD[1] Vccsp SP1ALLC Vss Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number K27 K28 K29 K30 K31 K32 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 M1 SP1AD[9] Vccsp SP1AVREFL[0] Vss SP1AVREFH[0] Vss HL3PD[9] Vss HL3PD[10] Vss HL3RQIN Vss Vcc Vcc Vcc Vcc Vcc Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc33 Vss Vcc Vss SP1ASTBP[1] Vss SP1ASTBN[1] Vss N/C Vss SP1AEP[2] Vss SP1AD[1] Vss Signal Ball Number M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 N1 N2 N3 N4 N5 N6 N7 N8 HL3PD[11] Vss HL3PD[12] Vss N/C Vcc Vss Vcc Vcc Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss SP0PRES Vss SP1ARSVD Vccsp SP1AD[10] Vss SP1ASTBP[0] Vccsp SP1ASTBN[0] Vss HL3PUSTRBS Vss HL3PUSTRBF Vss HL3STOP N/C Vss Vcc Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 N31 N32 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss SP1AD[11] Vss SP1ASSO Vss SP1AEP[1] Vss SP1AD[2] Vss SP1AD[3] Vss HL3PD[13] Vss HL3PD[14] Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Signal Ball Number P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 Vss Vcc Vss Vcc Vss Vcc Vss SP0SYNC Vccsp SP1AVREFH[3] Vss SP1AVREFL[3] Vccsp SP1AVREFH[1] Vss SP1AVREFL[1] Vss HL3PD[15] Vcc HL3PD[17] Vss HL3RQOUT N/C Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 Vss SP1AD[12] Vss SP1AD[15] Vss SP1AEP[0] Vss SP1AD[4] Vss SP1AD[7] Vss N/C Vss N/C HL3VREF[2] Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss SP0ZUPD[0] Vss SP1AD[13] Vccsp SP1AD[14] Vss SP1AD[6] Signal Ball Number T30 T31 T32 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 V1 V2 V3 V4 Vccsp SP1AD[5] Vss HL2PD[0] Vss HL2PD[1] Vcc HL2RCOMP HL2VREF[0] Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vss SP0BD[13] Vccsp SP0BD[14] Vss SP0BD[6] Vccsp SP0BD[5] Vss Vss HL2PD[2] Vss HL2PD[3] Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 Vss N/C Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss SP0ZUPD[1] SP0BD[12] Vss SP0BD[15] Vss SP0BEP[0] Vss SP0BD[4] Vss SP0BD[7] HL2PD[4] Vss HL2PSTRBS Vss HL2VSWING Vss Vss Vcc Vss Vcc Vss Signal Ball Number W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vccsp SP0BVREFH[3] Vss SP0BVREFL[3] Vccsp SP0BVREFH[1] Vss SP0BVREFL[1] Vss Vss HL2PSTRBF Vss HL2PD[5] Vcc N/C Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 Vcc Vss Vcc Vss SP0GPIO[0] SP0BD[11] Vss SP0BSSO Vss SP0BEP[1] Vss SP0BD[2] Vss SP0BD[3] HL2PD[6] Vss HL2PD[7] Vss HL2VREF[1] N/C Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc 330-ohm P/D Vss SP0BRSVD Signal Ball Number AA26 AA27 AA28 AA29 AA30 AA31 AA32 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AB32 Vccsp SP0BD[10] Vss SP0BSTBP[0] Vccsp SP0BSTBN[0] Vss Vcc HL2PD[16] Vcc HL2PD[8] Vss N/C N/C Vss Vss Vcc Vss Vss Vcc Vss Vcc Vss TDIOCATHODE Vss Vcc Vss Vcc Vss SP0GPIO[1] SP0BSTBP[1] Vss SP0BSTBN[1] Vss N/c Vss SP0BEP[2] Vss SP0BD[1] Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AD1 AD2 AD3 AD4 AD5 AD6 AD7 HL2PD[9] Vss HL2PD[10] Vss HL2RQIN Vss Vss Vss Vss Vss Vss Vcc Vss Vss Vss Vss SDA Vcc NODEID[0] NODEID[1] Vss INT_OUT# Vss Vccsp SP0BLLC Vss SP0BD[9] Vccsp SP0BVREFH[0] Vss SP0BVREFL[0] Vss Vss HL2PD[11] Vss HL2PD[12] Vss HL2VREF[2] Vss Signal Ball Number AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 Vcc Vss Vss Vss Vss Vss Vcc Vss SCL Vss 330-ohm P/D BUSID[2] Vcc N/C 300-ohm P/D SP1GPIO[0] SP0BVREFL[2] Vss SP0BVREFH[2] Vss N/C Vss SP0AD[0] Vss SP0BD[0] HL2PUSTRBS Vss HL2PUSTRBF Vss HL2STOP HL1VREF[0] Vss Vss Vss Vcc 300-ohm P/D Vss Vss Vss Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 ERR#[1] VCC33 Vss EVBPOUT# Vss N/C NODEID[2] Vcc SP1GPIO[1] Vss SP0BD[8] Vccsp N/C Vss SP0AVREFH[0] Vccsp SP0AVREFL[0] Vss Vss HL2PD[13] Vss HL2PD[14] Vcc Vss 330-ohm P/D 300-ohm P/D Vss 300-ohm P/D Vss Vcc Vss ERR#[0] Vss TDIOANODE BUSID[1] Vcc N/C N/C Vss Signal Ball Number AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 NODEID[3] Vss N/C Vss SP0AD[8] Vss SP0AEP[1] Vss SP0AD[1] Vss SP0AEP[2] HL2PD[15] Vcc HL2PD[17] Vss HL2RQOUT N/C N/C Vcc N/C HL1VREF[2] Vss ERR#[2] BUSID[0] Vcc ITEST 330-ohm P/D Vss RESETI# N/C Vcc N/C N/C NODEID[4] Vccsp SP0AVREFH[2] Vss SP0AVREFL[2] Vccsp Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number AG29 AG30 AG31 AG32 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AJ1 AJ2 AJ3 Signal SP0ASTBN[0] Vss SP0ASTBP[0] Vss Vss Vcc Vss Vcc Vss HL1RCOMP Vss HL1VSWING Vcc HL1VREF[1] Vss HL1RQIN Vss HL1STOP Vcc HL1RQOUT TDO TMS Vss N/C N/C Vcc EVBPIn# SP0AD[9] Vss SP0ALLC Vss SP0AEP[0] Vss SP0AD[3] Vss SP0AD[2] Vcc Vss Vcc Ball Number AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 Vss Vcc Vcc HL1PD[3] Vss HL1PD[5] Vss HL1PD[8] Vss HL1PD[12] Vss HL1PD[14] Vss TDI Vcc EV#[1] N/C Vss N/C N/C Vss SP0ASTBN[1] Vccsp SP0ASTBP[1] Vss SP0AVREFL[1] Vccsp SP0AVREFH[1] Vss Vss Vcc Vss Vcc Vss HL1PD[1] Vss HL1PSTRBS Vss HL1PD[7] Signal
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Table 9-1. SIOH Ball List (Continued)
Ball Number AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 Vcc HL1PD[10] Vss HL1PUSTRBF Vss HL1PD[17] TSO RESET66# EV#[2] Vcc N/C N/C Vss SP0AD[10] Vss SP0ARSVD Vss SP0AD[6] Vss SP0AD[7] Vss SP0AD[4] Vss Vcc Vss Vcc Vss HL1PD[2] Vss HL1PSTRBF Vss HL1PD[16] Vss HL1PD[11] Vss HL1PD[13] Vcc TRST# PWRGOOD Vss N/C Signal Ball Number AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 N/C Vcc SP0AD[14] Vccsp SP0AVREFL[3] Vss SP0AVREFH[3] Vccsp SP0AD[11] Vss SP0AD[5] Vss Vcc Vss HL1PD[0] Vss HL1PD[4] Vss HL1PD[6] Vcc HL1PD[9] Vss HL1PUSTRBS Vss HL1PD[15] TCK Vcc EV#[3] EV#[0] Vss N/C Vss SP0AD[13] Vss SP0AD[15] Vss SP0AD[12] Vss SP0ASSO Signal
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Signal - Ball Number List
Signal 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D 330-ohm P/D BUSID[0] BUSID[1] BUSID[2] CLK33 CLK66 DET ERR#[0] ERR#[1] ERR#[2] EV#[0] EV#[1] EV#[2] EV#[3] EVBPIn# EVBPOUT# FBCLK66 >= 1k-ohm P/D Ball Number G14 F14 F15 H16 AD18 G9 H8 J18 AE11 AF8 H13 G17 AD22 AF10 AF7 D23 H15 H9 AA23 AG16 AG13 AF17 AD19 F13 F11 G13 AF14 AE15 AG12 AM20 AJ19 AK19 AM19 AH23 AE18 J22 C17 HL0PAR# HL0PD[0]# HL0PD[1]# HL0PD[2]# HL0PD[3]# HL0PD[4]# HL0PD[5]# HL0PD[6]# HL0PD[7]# HL0PSTRBF HL0PSTRBS HL0RCOMP HL0RQIN# HL0RQOUT# HL0STOP# HL0VREF[0] HL0VREF[1] HL0VSWING HL1PD[0] HL1PD[1] HL1PD[10] HL1PD[11] HL1PD[12] HL1PD[13] HL1PD[14] HL1PD[15] HL1PD[16] HL1PD[17] HL1PD[2] HL1PD[3] HL1PD[4] HL1PD[5] HL1PD[6] HL1PD[7] HL1PD[8] HL1PD[9] HL1PSTRBF Signal Ball Number E20 A22 C22 B21 D21 C20 D19 A18 C18 B19 A20 E17 F18 F19 E18 B17 F21 F17 AM6 AK6 AK12 AL13 AJ13 AL15 AJ15 AM16 AL11 AK16 AL7 AJ7 AM8 AJ9 AM10 AK10 AJ11 AM12 AL9
Table 9-2. SIOH Signal - Ball Number
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal HL1PSTRBS HL1PUSTRBF HL1PUSTRBS HL1RCOMP HL1RQIN HL1RQOUT HL1STOP HL1VREF[0] HL1VREF[1] HL1VREF[2] HL1VSWING HL2PD[0] HL2PD[1] HL2PD[10] HL2PD[11] HL2PD[12] HL2PD[13] HL2PD[14] HL2PD[15] HL2PD[16] HL2PD[17] HL2PD[2] HL2PD[3] HL2PD[4] HL2PD[5] HL2PD[6] HL2PD[7] HL2PD[8] HL2PD[9] HL2PSTRBF HL2PSTRBS HL2PUSTRBF HL2PUSTRBS HL2RCOMP HL2RQIN HL2RQOUT HL2STOP HL2VREF[0] HL2VREF[1] Ball Number AK8 AK14 AM14 AH6 AH12 AH16 AH14 AE6 AH10 AG10 AH8 U1 U3 AC3 AD2 AD4 AF2 AF4 AG1 AB2 AG3 V2 V4 W1 Y4 AA1 AA3 AB4 AC1 Y2 W3 AE3 AE1 U5 AC5 AG5 AE5 U6 AA5 Signal HL2VREF[2] HL2VSWING HL3PD[0] HL3PD[1] HL3PD[10] HL3PD[11] HL3PD[12] HL3PD[13] HL3PD[14] HL3PD[15] HL3PD[16] HL3PD[17] HL3PD[2] HL3PD[3] HL3PD[4] HL3PD[5] HL3PD[6] HL3PD[7] HL3PD[8] HL3PD[9] HL3PSTRBF HL3PSTRBS HL3PUSTRBF HL3PUSTRBS HL3RCOMP HL3RQIN HL3RQOUT HL3STOP HL3VREF[0] HL3VREF[1] HL3VREF[2] HL3VSWING HL4PD[0] HL4PD[1] HL4PD[10] HL4PD[11] HL4PD[12] HL4PD[13] HL4PD[14] Ball Number AD6 W5 E1 E3 L3 M2 M4 P2 P4 R1 K2 R3 F2 F4 G1 H4 J1 J3 K4 L1 H2 G3 N3 N1 E5 L5 R5 N5 K6 J5 T5 G5 A16 C16 C10 B9 D9 B7 D7
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal HL4PD[15] HL4PD[16] HL4PD[17] HL4PD[2] HL4PD[3] HL4PD[4] HL4PD[5] HL4PD[6] HL4PD[7] HL4PD[8] HL4PD[9] HL4PSTRBF HL4PSTRBS HL4PUSTRBF HL4PUSTRBS HL4RCOMP HL4RQIN HL4RQOUT HL4STOP HL4VREF[0] HL4VREF[1] HL4VREF[2] HL4VSWING INT_OUT# ITEST LVHSTLODTEN N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C Ball Number A6 B11 C6 B15 D15 A14 D13 A12 C12 D11 A10 B13 C14 C8 A8 E16 E10 E6 E8 F9 E12 H6 E14 AC22 AG15 F10 AE20 AG22 AF19 AH20 AM22 AL21 AL20 AG19 AG21 AJ23 AJ22 AF20 AH21 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C NODEID[0] NODEID[1] NODEID[2] Signal Ball Number AK22 AK21 AJ20 E22 AG9 V6 Y6 AG6 AG7 AB6 G7 R6 M6 N6 F8 F6 AD21 AA6 AB7 AE27 AF24 G24 H27 T2 T4 H17 H12 H11 G16 G18 G10 G12 AD28 AB28 L28 J28 AC19 AC20 AE21
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal NODEID[3] NODEID[4] PWRGOOD RESET66# RESETI# SCL SDA SP0AD[0] SP0AD[1] SP0AD[10] SP0AD[11] SP0AD[12] SP0AD[13] SP0AD[14] SP0AD[15] SP0AD[2] SP0AD[3] SP0AD[4] SP0AD[5] SP0AD[6] SP0AD[7] SP0AD[8] SP0AD[9] SP0AEP[0] SP0AEP[1] SP0AEP[2] SP0ALLC SP0ARSVD SP0ASSO SP0ASTBN[0] SP0ASTBN[1] SP0ASTBP[0] SP0ASTBP[1] SP0AVREFH[0] SP0AVREFH[1] SP0AVREFH[2] SP0AVREFH[3] SP0AVREFL[0] SP0AVREFL[1] Ball Number AF22 AG23 AL18 AK18 AG18 AD16 AC17 AD30 AF30 AK24 AL29 AM28 AM24 AL23 AM26 AH32 AH30 AK32 AL31 AK28 AK30 AF26 AH24 AH28 AF28 AF32 AH26 AK26 AM30 AG29 AJ25 AG31 AJ27 AE29 AJ31 AG25 AL27 AE31 AJ29 Signal SP0AVREFL[2] SP0AVREFL[3] SP0BD[0] SP0BD[1] SP0BD[10] SP0BD[11] SP0BD[12] SP0BD[13] SP0BD[14] SP0BD[15] SP0BD[2] SP0BD[3] SP0BD[4] SP0BD[5] SP0BD[6] SP0BD[7] SP0BD[8] SP0BD[9] SP0BEP[0] SP0BEP[1] SP0BEP[2] SP0BLLC SP0BRSVD SP0BSSO SP0BSTBN[0] SP0BSTBN[1] SP0BSTBP[0] SP0BSTBP[1] SP0BVREFH[0] SP0BVREFH[1] SP0BVREFH[2] SP0BVREFH[3] SP0BVREFL[0] SP0BVREFL[1] SP0BVREFL[2] SP0BVREFL[3] SP0GPIO[0] SP0GPIO[1] SP0PRES Ball Number AG27 AL25 AD32 AB32 AA27 Y24 V24 U25 U27 V26 Y30 Y32 V30 U31 U29 V32 AE25 AC27 V28 Y28 AB30 AC25 AA25 Y26 AA31 AB26 AA29 AB24 AC29 W29 AD26 W25 AC31 W31 AD24 W27 Y23 AB23 M23
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal SP0SYNC SP0ZUPD[0] SP0ZUPD[1] SP1AD[0] SP1AD[1] SP1AD[10] SP1AD[11] SP1AD[12] SP1AD[13] SP1AD[14] SP1AD[15] SP1AD[2] SP1AD[3] SP1AD[4] SP1AD[5] SP1AD[6] SP1AD[7] SP1AD[8] SP1AD[9] SP1AEP[0] SP1AEP[1] SP1AEP[2] SP1ALLC SP1ARSVD SP1ASSO SP1ASTBN[0] SP1ASTBN[1] SP1ASTBP[0] SP1ASTBP[1] SP1AVREFH[0] SP1AVREFH[1] SP1AVREFH[2] SP1AVREFH[3] SP1AVREFL[0] SP1AVREFL[1] SP1AVREFL[2] SP1AVREFL[3] SP1BD[0] SP1BD[1] Ball Number P23 T23 V23 J32 L32 M27 N24 R24 T25 T27 R26 N30 N32 R30 T31 T29 R32 H25 K27 R28 N28 L30 K25 M25 N26 M31 L26 M29 L24 K31 P29 J26 P25 K29 P31 J24 P27 J30 G30 SP1BD[10] SP1BD[11] SP1BD[12] SP1BD[13] SP1BD[14] SP1BD[15] SP1BD[2] SP1BD[3] SP1BD[4] SP1BD[5] SP1BD[6] SP1BD[7] SP1BD[8] SP1BD[9] SP1BEP[0] SP1BEP[1] SP1BEP[2] SP1BLLC SP1BRSVD SP1BSSO SP1BSTBN[0] SP1BSTBN[1] SP1BSTBP[0] SP1BSTBP[1] SP1BVREFH[0] SP1BVREFH[1] SP1BVREFH[2] SP1BVREFH[3] SP1BVREFL[0] SP1BVREFL[1] SP1BVREFL[2] SP1BVREFL[3] SP1GPIO[0] SP1GPIO[1] SP1PRES SP1SYNC SP1ZUPD[0] SP1ZUPD[1] SYSCLK Signal Ball Number C24 B29 A28 A24 B23 A26 E32 E30 C32 B31 C28 C30 G26 E24 E28 G32 G28 E26 C26 A30 F29 D25 F31 D27 H29 D31 F25 B27 H31 D29 F27 B25 AD23 AE23 F23 G23 H23 K23 J20
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal SYSCLK# TCK TDI TDIOANODE TDIOCATHODE TDO TMS TRST# TSO Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Ball Number H19 AM17 AJ17 AF16 AB17 AH17 AH18 AL17 AK17 K18 H7 L11 J7 K7 M11 J11 K11 K15 J15 J12 J14 M7 L8 J10 K9 L9 M9 K10 M10 J8 L7 K14 K13 K17 J16 AE22 AF5 AF12 AF18 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Signal Ball Number AG2 AG8 AG14 AG20 AH2 AH4 AH9 AH15 AH22 AJ1 AJ3 AJ5 AJ6 A4 A11 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AB1 AB3 AB10 AB13 AB15 AB19 AB21 AC12 AC18 AD8 AD14 AD20 AE10 E4 E7 E13
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Ball Number G11 G15 H5 J9 J13 J17 K1 K3 L10 L12 L14 L16 L18 L22 AJ18 AK2 AK4 AK11 AK20 AL3 AL5 AL16 AL22 AM4 AM11 AM18 B3 B5 B6 C2 C4 C11 D1 D3 D5 D16 R2 R8 R10 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Signal Ball Number R12 R14 R16 R18 R20 R22 T7 T9 T11 T13 T15 T17 T19 T21 U4 U8 U10 M13 M15 M17 M19 M21 N8 N10 N12 N14 N16 N18 N20 N22 P5 P7 P9 P11 P13 P15 P17 P19 P21
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc18 Vcc18 Vcc18 Vcc18 Vcc18 Vcc33 Vcc33 Vcc33 Ball Number W18 W20 W22 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 Y21 U12 U14 U16 U18 U20 U22 V7 V9 V11 V13 V15 V17 V19 V21 W8 W10 W12 W14 W16 A17 C21 D18 F20 F22 AE16 K20 L20 VCCACOM VCCACORE VCCAHL VCCASP Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp Vccsp VREFFBCLK66 Vss Vss Signal Ball Number K19 G20 J19 H20 D30 F24 F28 H26 H30 K24 K28 M26 M30 P24 P28 T26 T30 U26 U30 W24 W28 AA26 AA30 AC24 AC28 AE26 AE30 AG24 AG28 AJ26 AJ30 AL24 AL28 B24 B28 D26 K22 AF11 AF13
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball Number AE9 AD7 AD10 AC7 AC8 AB8 AB9 AC10 AB11 AC11 AE8 AD9 AC16 AE14 AD15 AE12 AC14 AD13 AD12 AC13 A3 A5 A7 A9 A13 AA21 AA24 AA28 AA32 AB5 AB12 AB14 AB16 AB18 AB20 AB22 AB25 AB27 AB29 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Signal Ball Number AB31 AC2 AC4 AC6 AC9 AC15 AC21 AC23 AC26 A15 A19 A21 A23 A25 A27 A29 AA2 AA4 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AE19 AE24 AE28 AE32 AF1 AF3 AF6 AF9 AF15 AF21 AF23 AF25 AF27 AF29
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball Number AF31 AG4 AG11 AG17 AG26 AG30 AG32 AH1 AH3 AH5 AH7 AH11 AC30 AC32 AD1 AD3 AD5 AD11 AD17 AD25 AD27 AD29 AD31 AE2 AE4 AE7 AE13 AE17 AJ21 AJ24 AJ28 AJ32 AK1 AK3 AK5 AK7 AK9 AK13 AK15 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Signal Ball Number AK23 AK25 AK27 AK29 AK31 AL2 AL4 AL6 AL8 AL10 AL12 AL14 AL19 AL26 AL30 AH13 AH19 AH25 AH27 AH29 AH31 AJ2 AJ4 AJ8 AJ10 AJ12 AJ14 AJ16 B8 B10 B12 B14 B16 B18 B20 B22 B26 B30 C1
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball Number C3 C5 C7 C9 C13 C15 C19 C23 C25 C27 C29 C31 D2 D4 D6 D8 D10 D12 AM3 AM5 AM7 AM9 AM13 AM15 AM21 AM23 AM25 AM27 AM29 B2 B4 E15 E19 E21 E23 E25 E27 E29 E31 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Signal Ball Number F1 F3 F5 F7 F12 F16 F26 F30 F32 G2 G4 G6 G8 G19 G25 G27 G29 G31 H1 H3 H10 D14 D17 D20 D22 D24 D28 D32 E2 E9 E11 J23 J25 J27 J29 J31 K5 K8 K12
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball Number K16 K26 K30 K32 L2 L4 L6 L13 L15 L17 L19 L21 L23 L25 L27 L29 L31 M1 M3 M5 M8 M12 M14 M16 H14 H18 H22 H24 H28 H32 J2 J4 J6 J21 N4 N7 N9 N11 N13 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Signal Ball Number N15 N17 N19 N21 N23 N25 N27 N29 N31 P1 P3 P6 P8 P10 P12 P14 P16 P18 P20 P22 P26 P30 P32 R4 R7 R9 R11 M18 M20 M22 M24 M28 M32 N2 R27 R29 R31 T1 T3
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Table 9-2. SIOH Signal - Ball Number (Continued)
Signal Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball Number T6 T8 T10 T12 T14 T16 T18 T20 T22 T24 T28 T32 U2 U7 U9 U11 U13 U15 U17 U19 U21 U23 U24 U28 U32 V1 V3 V5 V8 V10 R13 R15 R17 R19 R21 R23 R25 V20 V22 V25 V27 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss VSSACOM VSSACORE VSSAHL VSSASP Signal Ball Number V29 V31 W2 W4 W6 W7 W9 W11 W13 W15 W17 W19 W21 W23 W26 W30 W32 Y1 Y3 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Y22 Y25 Y27 Y29 Y31 V12 V14 V16 V18 K21 G21 G22 H21
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